mirror of https://gerrit.osmocom.org/libusrp
766 lines
23 KiB
Verilog
Executable File
766 lines
23 KiB
Verilog
Executable File
// megafunction wizard: %ALTACCUMULATE%CBX%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altaccumulate
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// ============================================================
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// File Name: accum32.v
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// Megafunction Name(s):
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// altaccumulate
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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//Copyright (C) 1991-2003 Altera Corporation
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//Any megafunction design, and related netlist (encrypted or decrypted),
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//support information, device programming or simulation file, and any other
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//associated documentation or information provided by Altera or a partner
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//under Altera's Megafunction Partnership Program may be used only
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//to program PLD devices (but not masked PLD devices) from Altera. Any
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//other use of such megafunction design, netlist, support information,
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//device programming or simulation file, or any other related documentation
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//or information is prohibited for any other purpose, including, but not
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//limited to modification, reverse engineering, de-compiling, or use with
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//any other silicon devices, unless such use is explicitly licensed under
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//a separate agreement with Altera or a megafunction partner. Title to the
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//intellectual property, including patents, copyrights, trademarks, trade
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//secrets, or maskworks, embodied in any such megafunction design, netlist,
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//support information, device programming or simulation file, or any other
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//related documentation or information provided by Altera or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
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//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
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//synthesis_resources = lut 32
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module accum32_accum_nta
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(
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aclr,
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clken,
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clock,
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data,
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result) /* synthesis synthesis_clearbox=1 */;
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input aclr;
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input clken;
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input clock;
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input [31:0] data;
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output [31:0] result;
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wire [0:0] wire_acc_cella_0cout;
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wire [0:0] wire_acc_cella_1cout;
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wire [0:0] wire_acc_cella_2cout;
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wire [0:0] wire_acc_cella_3cout;
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wire [0:0] wire_acc_cella_4cout;
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wire [0:0] wire_acc_cella_5cout;
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wire [0:0] wire_acc_cella_6cout;
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wire [0:0] wire_acc_cella_7cout;
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wire [0:0] wire_acc_cella_8cout;
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wire [0:0] wire_acc_cella_9cout;
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wire [0:0] wire_acc_cella_10cout;
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wire [0:0] wire_acc_cella_11cout;
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wire [0:0] wire_acc_cella_12cout;
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wire [0:0] wire_acc_cella_13cout;
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wire [0:0] wire_acc_cella_14cout;
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wire [0:0] wire_acc_cella_15cout;
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wire [0:0] wire_acc_cella_16cout;
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wire [0:0] wire_acc_cella_17cout;
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wire [0:0] wire_acc_cella_18cout;
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wire [0:0] wire_acc_cella_19cout;
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wire [0:0] wire_acc_cella_20cout;
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wire [0:0] wire_acc_cella_21cout;
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wire [0:0] wire_acc_cella_22cout;
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wire [0:0] wire_acc_cella_23cout;
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wire [0:0] wire_acc_cella_24cout;
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wire [0:0] wire_acc_cella_25cout;
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wire [0:0] wire_acc_cella_26cout;
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wire [0:0] wire_acc_cella_27cout;
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wire [0:0] wire_acc_cella_28cout;
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wire [0:0] wire_acc_cella_29cout;
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wire [0:0] wire_acc_cella_30cout;
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wire [31:0] wire_acc_cella_dataa;
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wire [31:0] wire_acc_cella_datab;
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wire [31:0] wire_acc_cella_datac;
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wire [31:0] wire_acc_cella_regout;
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wire sload;
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stratix_lcell acc_cella_0
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(
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.aclr(aclr),
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.cin(1'b0),
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.clk(clock),
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.cout(wire_acc_cella_0cout[0:0]),
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.dataa(wire_acc_cella_dataa[0:0]),
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.datab(wire_acc_cella_datab[0:0]),
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.datac(wire_acc_cella_datac[0:0]),
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.ena(clken),
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.regout(wire_acc_cella_regout[0:0]),
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.sload(sload));
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defparam
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acc_cella_0.cin_used = "true",
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acc_cella_0.lut_mask = "96e8",
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acc_cella_0.operation_mode = "arithmetic",
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acc_cella_0.sum_lutc_input = "cin",
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acc_cella_0.synch_mode = "on",
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acc_cella_0.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_1
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(
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.aclr(aclr),
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.cin(wire_acc_cella_0cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_1cout[0:0]),
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.dataa(wire_acc_cella_dataa[1:1]),
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.datab(wire_acc_cella_datab[1:1]),
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.datac(wire_acc_cella_datac[1:1]),
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.ena(clken),
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.regout(wire_acc_cella_regout[1:1]),
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.sload(sload));
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defparam
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acc_cella_1.cin_used = "true",
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acc_cella_1.lut_mask = "96e8",
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acc_cella_1.operation_mode = "arithmetic",
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acc_cella_1.sum_lutc_input = "cin",
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acc_cella_1.synch_mode = "on",
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acc_cella_1.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_2
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(
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.aclr(aclr),
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.cin(wire_acc_cella_1cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_2cout[0:0]),
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.dataa(wire_acc_cella_dataa[2:2]),
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.datab(wire_acc_cella_datab[2:2]),
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.datac(wire_acc_cella_datac[2:2]),
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.ena(clken),
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.regout(wire_acc_cella_regout[2:2]),
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.sload(sload));
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defparam
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acc_cella_2.cin_used = "true",
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acc_cella_2.lut_mask = "96e8",
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acc_cella_2.operation_mode = "arithmetic",
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acc_cella_2.sum_lutc_input = "cin",
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acc_cella_2.synch_mode = "on",
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acc_cella_2.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_3
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(
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.aclr(aclr),
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.cin(wire_acc_cella_2cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_3cout[0:0]),
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.dataa(wire_acc_cella_dataa[3:3]),
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.datab(wire_acc_cella_datab[3:3]),
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.datac(wire_acc_cella_datac[3:3]),
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.ena(clken),
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.regout(wire_acc_cella_regout[3:3]),
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.sload(sload));
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defparam
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acc_cella_3.cin_used = "true",
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acc_cella_3.lut_mask = "96e8",
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acc_cella_3.operation_mode = "arithmetic",
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acc_cella_3.sum_lutc_input = "cin",
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acc_cella_3.synch_mode = "on",
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acc_cella_3.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_4
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(
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.aclr(aclr),
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.cin(wire_acc_cella_3cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_4cout[0:0]),
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.dataa(wire_acc_cella_dataa[4:4]),
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.datab(wire_acc_cella_datab[4:4]),
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.datac(wire_acc_cella_datac[4:4]),
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.ena(clken),
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.regout(wire_acc_cella_regout[4:4]),
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.sload(sload));
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defparam
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acc_cella_4.cin_used = "true",
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acc_cella_4.lut_mask = "96e8",
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acc_cella_4.operation_mode = "arithmetic",
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acc_cella_4.sum_lutc_input = "cin",
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acc_cella_4.synch_mode = "on",
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acc_cella_4.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_5
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(
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.aclr(aclr),
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.cin(wire_acc_cella_4cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_5cout[0:0]),
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.dataa(wire_acc_cella_dataa[5:5]),
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.datab(wire_acc_cella_datab[5:5]),
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.datac(wire_acc_cella_datac[5:5]),
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.ena(clken),
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.regout(wire_acc_cella_regout[5:5]),
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.sload(sload));
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defparam
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acc_cella_5.cin_used = "true",
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acc_cella_5.lut_mask = "96e8",
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acc_cella_5.operation_mode = "arithmetic",
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acc_cella_5.sum_lutc_input = "cin",
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acc_cella_5.synch_mode = "on",
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acc_cella_5.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_6
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(
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.aclr(aclr),
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.cin(wire_acc_cella_5cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_6cout[0:0]),
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.dataa(wire_acc_cella_dataa[6:6]),
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.datab(wire_acc_cella_datab[6:6]),
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.datac(wire_acc_cella_datac[6:6]),
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.ena(clken),
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.regout(wire_acc_cella_regout[6:6]),
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.sload(sload));
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defparam
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acc_cella_6.cin_used = "true",
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acc_cella_6.lut_mask = "96e8",
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acc_cella_6.operation_mode = "arithmetic",
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acc_cella_6.sum_lutc_input = "cin",
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acc_cella_6.synch_mode = "on",
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acc_cella_6.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_7
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(
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.aclr(aclr),
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.cin(wire_acc_cella_6cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_7cout[0:0]),
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.dataa(wire_acc_cella_dataa[7:7]),
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.datab(wire_acc_cella_datab[7:7]),
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.datac(wire_acc_cella_datac[7:7]),
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.ena(clken),
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.regout(wire_acc_cella_regout[7:7]),
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.sload(sload));
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defparam
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acc_cella_7.cin_used = "true",
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acc_cella_7.lut_mask = "96e8",
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acc_cella_7.operation_mode = "arithmetic",
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acc_cella_7.sum_lutc_input = "cin",
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acc_cella_7.synch_mode = "on",
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acc_cella_7.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_8
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(
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.aclr(aclr),
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.cin(wire_acc_cella_7cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_8cout[0:0]),
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.dataa(wire_acc_cella_dataa[8:8]),
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.datab(wire_acc_cella_datab[8:8]),
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.datac(wire_acc_cella_datac[8:8]),
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.ena(clken),
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.regout(wire_acc_cella_regout[8:8]),
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.sload(sload));
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defparam
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acc_cella_8.cin_used = "true",
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acc_cella_8.lut_mask = "96e8",
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acc_cella_8.operation_mode = "arithmetic",
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acc_cella_8.sum_lutc_input = "cin",
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acc_cella_8.synch_mode = "on",
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acc_cella_8.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_9
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(
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.aclr(aclr),
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.cin(wire_acc_cella_8cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_9cout[0:0]),
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.dataa(wire_acc_cella_dataa[9:9]),
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.datab(wire_acc_cella_datab[9:9]),
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.datac(wire_acc_cella_datac[9:9]),
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.ena(clken),
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.regout(wire_acc_cella_regout[9:9]),
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.sload(sload));
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defparam
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acc_cella_9.cin_used = "true",
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acc_cella_9.lut_mask = "96e8",
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acc_cella_9.operation_mode = "arithmetic",
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acc_cella_9.sum_lutc_input = "cin",
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acc_cella_9.synch_mode = "on",
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acc_cella_9.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_10
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(
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.aclr(aclr),
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.cin(wire_acc_cella_9cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_10cout[0:0]),
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.dataa(wire_acc_cella_dataa[10:10]),
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.datab(wire_acc_cella_datab[10:10]),
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.datac(wire_acc_cella_datac[10:10]),
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.ena(clken),
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.regout(wire_acc_cella_regout[10:10]),
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.sload(sload));
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defparam
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acc_cella_10.cin_used = "true",
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acc_cella_10.lut_mask = "96e8",
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acc_cella_10.operation_mode = "arithmetic",
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acc_cella_10.sum_lutc_input = "cin",
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acc_cella_10.synch_mode = "on",
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acc_cella_10.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_11
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(
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.aclr(aclr),
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.cin(wire_acc_cella_10cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_11cout[0:0]),
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.dataa(wire_acc_cella_dataa[11:11]),
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.datab(wire_acc_cella_datab[11:11]),
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.datac(wire_acc_cella_datac[11:11]),
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.ena(clken),
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.regout(wire_acc_cella_regout[11:11]),
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.sload(sload));
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defparam
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acc_cella_11.cin_used = "true",
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acc_cella_11.lut_mask = "96e8",
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acc_cella_11.operation_mode = "arithmetic",
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acc_cella_11.sum_lutc_input = "cin",
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acc_cella_11.synch_mode = "on",
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acc_cella_11.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_12
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(
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.aclr(aclr),
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.cin(wire_acc_cella_11cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_12cout[0:0]),
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.dataa(wire_acc_cella_dataa[12:12]),
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.datab(wire_acc_cella_datab[12:12]),
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.datac(wire_acc_cella_datac[12:12]),
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.ena(clken),
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.regout(wire_acc_cella_regout[12:12]),
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.sload(sload));
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defparam
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acc_cella_12.cin_used = "true",
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acc_cella_12.lut_mask = "96e8",
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acc_cella_12.operation_mode = "arithmetic",
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acc_cella_12.sum_lutc_input = "cin",
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acc_cella_12.synch_mode = "on",
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acc_cella_12.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_13
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(
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.aclr(aclr),
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.cin(wire_acc_cella_12cout[0:0]),
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.clk(clock),
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.cout(wire_acc_cella_13cout[0:0]),
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.dataa(wire_acc_cella_dataa[13:13]),
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.datab(wire_acc_cella_datab[13:13]),
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.datac(wire_acc_cella_datac[13:13]),
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.ena(clken),
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.regout(wire_acc_cella_regout[13:13]),
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.sload(sload));
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defparam
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acc_cella_13.cin_used = "true",
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acc_cella_13.lut_mask = "96e8",
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acc_cella_13.operation_mode = "arithmetic",
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acc_cella_13.sum_lutc_input = "cin",
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acc_cella_13.synch_mode = "on",
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acc_cella_13.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_14
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(
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.aclr(aclr),
|
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.cin(wire_acc_cella_13cout[0:0]),
|
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.clk(clock),
|
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.cout(wire_acc_cella_14cout[0:0]),
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.dataa(wire_acc_cella_dataa[14:14]),
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.datab(wire_acc_cella_datab[14:14]),
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.datac(wire_acc_cella_datac[14:14]),
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.ena(clken),
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.regout(wire_acc_cella_regout[14:14]),
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.sload(sload));
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defparam
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acc_cella_14.cin_used = "true",
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acc_cella_14.lut_mask = "96e8",
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acc_cella_14.operation_mode = "arithmetic",
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acc_cella_14.sum_lutc_input = "cin",
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acc_cella_14.synch_mode = "on",
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acc_cella_14.lpm_type = "stratix_lcell";
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stratix_lcell acc_cella_15
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(
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.aclr(aclr),
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.cin(wire_acc_cella_14cout[0:0]),
|
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.clk(clock),
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.cout(wire_acc_cella_15cout[0:0]),
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.dataa(wire_acc_cella_dataa[15:15]),
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.datab(wire_acc_cella_datab[15:15]),
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.datac(wire_acc_cella_datac[15:15]),
|
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.ena(clken),
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.regout(wire_acc_cella_regout[15:15]),
|
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.sload(sload));
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defparam
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acc_cella_15.cin_used = "true",
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acc_cella_15.lut_mask = "96e8",
|
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acc_cella_15.operation_mode = "arithmetic",
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acc_cella_15.sum_lutc_input = "cin",
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acc_cella_15.synch_mode = "on",
|
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acc_cella_15.lpm_type = "stratix_lcell";
|
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stratix_lcell acc_cella_16
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(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_15cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_16cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[16:16]),
|
|
.datab(wire_acc_cella_datab[16:16]),
|
|
.datac(wire_acc_cella_datac[16:16]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[16:16]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_16.cin_used = "true",
|
|
acc_cella_16.lut_mask = "96e8",
|
|
acc_cella_16.operation_mode = "arithmetic",
|
|
acc_cella_16.sum_lutc_input = "cin",
|
|
acc_cella_16.synch_mode = "on",
|
|
acc_cella_16.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_17
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_16cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_17cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[17:17]),
|
|
.datab(wire_acc_cella_datab[17:17]),
|
|
.datac(wire_acc_cella_datac[17:17]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[17:17]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_17.cin_used = "true",
|
|
acc_cella_17.lut_mask = "96e8",
|
|
acc_cella_17.operation_mode = "arithmetic",
|
|
acc_cella_17.sum_lutc_input = "cin",
|
|
acc_cella_17.synch_mode = "on",
|
|
acc_cella_17.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_18
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_17cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_18cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[18:18]),
|
|
.datab(wire_acc_cella_datab[18:18]),
|
|
.datac(wire_acc_cella_datac[18:18]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[18:18]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_18.cin_used = "true",
|
|
acc_cella_18.lut_mask = "96e8",
|
|
acc_cella_18.operation_mode = "arithmetic",
|
|
acc_cella_18.sum_lutc_input = "cin",
|
|
acc_cella_18.synch_mode = "on",
|
|
acc_cella_18.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_19
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_18cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_19cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[19:19]),
|
|
.datab(wire_acc_cella_datab[19:19]),
|
|
.datac(wire_acc_cella_datac[19:19]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[19:19]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_19.cin_used = "true",
|
|
acc_cella_19.lut_mask = "96e8",
|
|
acc_cella_19.operation_mode = "arithmetic",
|
|
acc_cella_19.sum_lutc_input = "cin",
|
|
acc_cella_19.synch_mode = "on",
|
|
acc_cella_19.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_20
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_19cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_20cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[20:20]),
|
|
.datab(wire_acc_cella_datab[20:20]),
|
|
.datac(wire_acc_cella_datac[20:20]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[20:20]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_20.cin_used = "true",
|
|
acc_cella_20.lut_mask = "96e8",
|
|
acc_cella_20.operation_mode = "arithmetic",
|
|
acc_cella_20.sum_lutc_input = "cin",
|
|
acc_cella_20.synch_mode = "on",
|
|
acc_cella_20.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_21
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_20cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_21cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[21:21]),
|
|
.datab(wire_acc_cella_datab[21:21]),
|
|
.datac(wire_acc_cella_datac[21:21]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[21:21]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_21.cin_used = "true",
|
|
acc_cella_21.lut_mask = "96e8",
|
|
acc_cella_21.operation_mode = "arithmetic",
|
|
acc_cella_21.sum_lutc_input = "cin",
|
|
acc_cella_21.synch_mode = "on",
|
|
acc_cella_21.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_22
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_21cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_22cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[22:22]),
|
|
.datab(wire_acc_cella_datab[22:22]),
|
|
.datac(wire_acc_cella_datac[22:22]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[22:22]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_22.cin_used = "true",
|
|
acc_cella_22.lut_mask = "96e8",
|
|
acc_cella_22.operation_mode = "arithmetic",
|
|
acc_cella_22.sum_lutc_input = "cin",
|
|
acc_cella_22.synch_mode = "on",
|
|
acc_cella_22.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_23
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_22cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_23cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[23:23]),
|
|
.datab(wire_acc_cella_datab[23:23]),
|
|
.datac(wire_acc_cella_datac[23:23]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[23:23]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_23.cin_used = "true",
|
|
acc_cella_23.lut_mask = "96e8",
|
|
acc_cella_23.operation_mode = "arithmetic",
|
|
acc_cella_23.sum_lutc_input = "cin",
|
|
acc_cella_23.synch_mode = "on",
|
|
acc_cella_23.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_24
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_23cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_24cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[24:24]),
|
|
.datab(wire_acc_cella_datab[24:24]),
|
|
.datac(wire_acc_cella_datac[24:24]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[24:24]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_24.cin_used = "true",
|
|
acc_cella_24.lut_mask = "96e8",
|
|
acc_cella_24.operation_mode = "arithmetic",
|
|
acc_cella_24.sum_lutc_input = "cin",
|
|
acc_cella_24.synch_mode = "on",
|
|
acc_cella_24.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_25
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_24cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_25cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[25:25]),
|
|
.datab(wire_acc_cella_datab[25:25]),
|
|
.datac(wire_acc_cella_datac[25:25]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[25:25]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_25.cin_used = "true",
|
|
acc_cella_25.lut_mask = "96e8",
|
|
acc_cella_25.operation_mode = "arithmetic",
|
|
acc_cella_25.sum_lutc_input = "cin",
|
|
acc_cella_25.synch_mode = "on",
|
|
acc_cella_25.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_26
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_25cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_26cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[26:26]),
|
|
.datab(wire_acc_cella_datab[26:26]),
|
|
.datac(wire_acc_cella_datac[26:26]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[26:26]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_26.cin_used = "true",
|
|
acc_cella_26.lut_mask = "96e8",
|
|
acc_cella_26.operation_mode = "arithmetic",
|
|
acc_cella_26.sum_lutc_input = "cin",
|
|
acc_cella_26.synch_mode = "on",
|
|
acc_cella_26.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_27
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_26cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_27cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[27:27]),
|
|
.datab(wire_acc_cella_datab[27:27]),
|
|
.datac(wire_acc_cella_datac[27:27]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[27:27]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_27.cin_used = "true",
|
|
acc_cella_27.lut_mask = "96e8",
|
|
acc_cella_27.operation_mode = "arithmetic",
|
|
acc_cella_27.sum_lutc_input = "cin",
|
|
acc_cella_27.synch_mode = "on",
|
|
acc_cella_27.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_28
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_27cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_28cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[28:28]),
|
|
.datab(wire_acc_cella_datab[28:28]),
|
|
.datac(wire_acc_cella_datac[28:28]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[28:28]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_28.cin_used = "true",
|
|
acc_cella_28.lut_mask = "96e8",
|
|
acc_cella_28.operation_mode = "arithmetic",
|
|
acc_cella_28.sum_lutc_input = "cin",
|
|
acc_cella_28.synch_mode = "on",
|
|
acc_cella_28.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_29
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_28cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_29cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[29:29]),
|
|
.datab(wire_acc_cella_datab[29:29]),
|
|
.datac(wire_acc_cella_datac[29:29]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[29:29]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_29.cin_used = "true",
|
|
acc_cella_29.lut_mask = "96e8",
|
|
acc_cella_29.operation_mode = "arithmetic",
|
|
acc_cella_29.sum_lutc_input = "cin",
|
|
acc_cella_29.synch_mode = "on",
|
|
acc_cella_29.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_30
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_29cout[0:0]),
|
|
.clk(clock),
|
|
.cout(wire_acc_cella_30cout[0:0]),
|
|
.dataa(wire_acc_cella_dataa[30:30]),
|
|
.datab(wire_acc_cella_datab[30:30]),
|
|
.datac(wire_acc_cella_datac[30:30]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[30:30]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_30.cin_used = "true",
|
|
acc_cella_30.lut_mask = "96e8",
|
|
acc_cella_30.operation_mode = "arithmetic",
|
|
acc_cella_30.sum_lutc_input = "cin",
|
|
acc_cella_30.synch_mode = "on",
|
|
acc_cella_30.lpm_type = "stratix_lcell";
|
|
stratix_lcell acc_cella_31
|
|
(
|
|
.aclr(aclr),
|
|
.cin(wire_acc_cella_30cout[0:0]),
|
|
.clk(clock),
|
|
.dataa(wire_acc_cella_dataa[31:31]),
|
|
.datab(wire_acc_cella_datab[31:31]),
|
|
.datac(wire_acc_cella_datac[31:31]),
|
|
.ena(clken),
|
|
.regout(wire_acc_cella_regout[31:31]),
|
|
.sload(sload));
|
|
defparam
|
|
acc_cella_31.cin_used = "true",
|
|
acc_cella_31.lut_mask = "9696",
|
|
acc_cella_31.operation_mode = "normal",
|
|
acc_cella_31.sum_lutc_input = "cin",
|
|
acc_cella_31.synch_mode = "on",
|
|
acc_cella_31.lpm_type = "stratix_lcell";
|
|
assign
|
|
wire_acc_cella_dataa = data,
|
|
wire_acc_cella_datab = wire_acc_cella_regout,
|
|
wire_acc_cella_datac = data;
|
|
assign
|
|
result = wire_acc_cella_regout,
|
|
sload = 1'b0;
|
|
endmodule //accum32_accum_nta
|
|
//VALID FILE
|
|
|
|
|
|
module accum32 (
|
|
data,
|
|
clock,
|
|
clken,
|
|
aclr,
|
|
result)/* synthesis synthesis_clearbox = 1 */;
|
|
|
|
input [31:0] data;
|
|
input clock;
|
|
input clken;
|
|
input aclr;
|
|
output [31:0] result;
|
|
|
|
wire [31:0] sub_wire0;
|
|
wire [31:0] result = sub_wire0[31:0];
|
|
|
|
accum32_accum_nta accum32_accum_nta_component (
|
|
.clken (clken),
|
|
.aclr (aclr),
|
|
.clock (clock),
|
|
.data (data),
|
|
.result (sub_wire0));
|
|
|
|
endmodule
|
|
|
|
// ============================================================
|
|
// CNX file retrieval info
|
|
// ============================================================
|
|
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
|
|
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
|
|
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
|
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
|
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
|
|
// Retrieval info: PRIVATE: CIN NUMERIC "0"
|
|
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
|
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
|
// Retrieval info: PRIVATE: COUT NUMERIC "0"
|
|
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
|
|
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
|
|
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
|
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
|
|
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
|
|
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
|
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
|
|
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
|
|
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
|
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
|
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
|
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
|
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|