mirror of https://gerrit.osmocom.org/libusrp
184 lines
4.4 KiB
Verilog
Executable File
184 lines
4.4 KiB
Verilog
Executable File
module tx_buffer_inband
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( input usbclk,
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input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
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input reset, // standard DSP-side reset
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input [15:0] usbdata,
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input wire WR,
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output wire have_space,
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output reg tx_underrun,
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input wire [3:0] channels,
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output [15:0] tx_i_0,
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output [15:0] tx_q_0,
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output [15:0] tx_i_1,
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output [15:0] tx_q_1,
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//NOT USED
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output reg [15:0] tx_i_2,
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output reg [15:0] tx_q_2,
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output reg [15:0] tx_i_3,
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output reg [15:0] tx_q_3,
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input txclk,
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input txstrobe,
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input clear_status,
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output wire tx_empty,
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output [11:0] debugbus
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);
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wire [15:0] tx_data_bus;
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wire WR_chan_0;
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wire chan_0_done;
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wire OR0;
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wire UR0;
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wire WR_chan_1;
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wire chan_1_done;
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wire OR1;
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wire UR1;
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// NOT USED yet
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wire WR_cmd;
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wire cmd_done;
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//EXTERNAL REGISTER
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//TODO: increment it
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reg [31:0] time_counter;
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reg [7:0] txstrobe_rate_0;
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reg [7:0] txstrobe_rate_1;
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//Usb block
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wire [15:0] tupf_fifodata;
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wire tupf_pkt_waiting;
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wire tupf_rdreq;
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wire tupf_skip;
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wire tupf_have_space;
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usb_packet_fifo2 tx_usb_packet_fifo
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( .reset (reset),
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.usb_clock (usbclk),
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.fpga_clock (txclk),
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.write_data (usbdata),
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.write_enable (WR),
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.read_data (tupf_fifodata),
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.pkt_waiting (tupf_pkt_waiting),
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.read_enable (tupf_rdreq),
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.skip_packet (tupf_skip),
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.have_space (tupf_have_space),
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.tx_empty (tx_empty)
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);
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usb_fifo_reader tx_usb_packet_reader (
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.reset(reset),
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.tx_clock(txclk),
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.tx_data_bus(tx_data_bus),
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.WR_chan_0(WR_chan_0),
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.WR_chan_1(WR_chan_1),
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.WR_cmd(WR_cmd),
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.chan_0_done(chan_0_done),
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.chan_1_done(chan_1_done),
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.cmd_done(cmd_done),
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.rdreq(tupf_rdreq),
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.skip(tupf_skip),
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.pkt_waiting(tupf_pkt_waiting),
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.fifodata(tupf_fifodata)
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);
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//Channel 0 block
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wire [15:0] tdpf_fifodata_0;
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wire tdpf_pkt_waiting_0;
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wire tdpf_rdreq_0;
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wire tdpf_skip_0;
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wire tdpf_have_space_0;
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wire txstrobe_chan_0;
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data_packet_fifo tx_data_packet_fifo_0
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( .reset(reset),
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.clock(txclk),
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.ram_data_in(tx_data_bus),
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.write_enable(WR_chan_0),
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.ram_data_out(tdpf_fifodata_0),
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.pkt_waiting(tdpf_pkt_waiting_0),
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.read_enable(tdpf_rdreq_0),
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.pkt_complete(chan_0_done),
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.skip_packet(tdpf_skip_0),
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.have_space(tdpf_have_space_0)
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);
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strobe_gen strobe_gen_0
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( .clock(txclk),
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.reset(reset),
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.enable(1'b1),
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.rate(txstrobe_rate_0),
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.strobe_in(txstrobe),
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.strobe(txstrobe_chan_0)
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);
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chan_fifo_reader tx_chan_0_reader (
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.reset(reset),
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.tx_clock(txclk),
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.tx_strobe(txstrobe),
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//.tx_strobe(txstrobe_chan_0),
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.adc_clock(time_counter),
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.samples_format(4'b0),
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.tx_q(tx_q_0),
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.tx_i(tx_i_0),
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.overrun(OR0),
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.underrun(UR0),
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.skip(tdpf_skip_0),
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.rdreq(tdpf_rdreq_0),
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.fifodata(tdpf_fifodata_0),
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.pkt_waiting(tdpf_pkt_waiting_0)
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);
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//Channel 1 block
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wire [15:0] tdpf_fifodata_1;
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wire tdpf_pkt_waiting_1;
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wire tdpf_rdreq_1;
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wire tdpf_skip_1;
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wire tdpf_have_space_1;
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wire txstrobe_chan_1;
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data_packet_fifo tx_data_packet_fifo_1
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( .reset(reset),
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.clock(txclk),
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.ram_data_in(tx_data_bus),
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.write_enable(WR_chan_1),
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.ram_data_out(tdpf_fifodata_1),
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.pkt_waiting(tdpf_pkt_waiting_1),
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.read_enable(tdpf_rdreq_1),
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.pkt_complete(chan_1_done),
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.skip_packet(tdpf_skip_1),
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.have_space(tdpf_have_space_1)
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);
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strobe_gen strobe_gen_1
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( .clock(txclk),
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.reset(reset),
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.enable(1'b1),
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.rate(txstrobe_rate_1),
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.strobe_in(txstrobe),
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.strobe(txstrobe_chan_1)
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);
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chan_fifo_reader tx_chan_1_reader (
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.reset(reset),
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.tx_clock(txclk),
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.tx_strobe(txstrobe),
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//.tx_strobe(txstrobe_chan_1),
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.adc_clock(time_counter),
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.samples_format(4'b0),
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.tx_q(tx_q_1),
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.tx_i(tx_i_1),
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.overrun(OR1),
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.underrun(UR1),
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.skip(tdpf_skip_1),
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.rdreq(tdpf_rdreq_1),
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.fifodata(tdpf_fifodata_1),
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.pkt_waiting(tdpf_pkt_waiting_1)
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);
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endmodule // tx_buffer
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