mirror of https://gerrit.osmocom.org/libusrp
129 lines
3.7 KiB
Verilog
Executable File
129 lines
3.7 KiB
Verilog
Executable File
module data_packet_fifo
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( input reset,
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input clock,
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input [15:0]ram_data_in,
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input write_enable,
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output reg have_space,
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output reg [15:0]ram_data_out,
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output reg pkt_waiting,
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input read_enable,
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input pkt_complete,
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input skip_packet) ;
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/* Some parameters for usage later on */
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parameter DATA_WIDTH = 16 ;
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parameter NUM_PACKETS = 4 ;
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/* Create the RAM here */
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reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
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/* Create the address signals */
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reg [7:0] usb_ram_offset_out ;
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reg [1:0] usb_ram_packet_out ;
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reg [7:0] usb_ram_offset_in ;
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reg [1:0] usb_ram_packet_in ;
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wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
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wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
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reg isfull;
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assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
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assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
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// Check if there is one full packet to process
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always @(usb_ram_ain, usb_ram_aout)
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begin
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if (reset)
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pkt_waiting <= 0;
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else if (usb_ram_ain >= usb_ram_aout)
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pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
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else
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pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
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end
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// Check if there is room
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always @(usb_ram_ain, usb_ram_aout)
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begin
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if (reset)
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have_space <= 1;
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else if (usb_ram_ain == usb_ram_aout)
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have_space <= ~isfull;
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else if (usb_ram_ain > usb_ram_aout)
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have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
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else
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have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
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end
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/* RAM Write Address process */
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always @(posedge clock)
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begin
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if( reset )
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begin
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usb_ram_offset_in <= 0 ;
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usb_ram_packet_in <= 0 ;
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end
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else
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if( pkt_complete )
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begin
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usb_ram_packet_in <= usb_ram_packet_in + 1;
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usb_ram_offset_in <= 0;
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end
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else if( write_enable )
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begin
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if (usb_ram_offset_in == 8'b11111111)
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begin
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usb_ram_offset_in <= 0;
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usb_ram_packet_in <= usb_ram_packet_in + 1;
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end
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else
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usb_ram_offset_in <= usb_ram_offset_in + 1 ;
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if (usb_ram_ain + 1 == usb_ram_aout)
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isfull <= 1;
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end
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end
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/* RAM Writing process */
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always @(posedge clock)
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begin
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if( write_enable )
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begin
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usb_ram[usb_ram_ain] <= ram_data_in ;
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end
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end
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/* RAM Read Address process */
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always @(posedge clock)
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begin
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if( reset )
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begin
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usb_ram_packet_out <= 0 ;
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usb_ram_offset_out <= 0 ;
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isfull <= 0;
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end
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else
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if( skip_packet )
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begin
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usb_ram_packet_out <= usb_ram_packet_out + 1 ;
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usb_ram_offset_out <= 0 ;
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end
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else if(read_enable) begin
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if( usb_ram_offset_out == 8'b11111111 )
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begin
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usb_ram_offset_out <= 0 ;
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usb_ram_packet_out <= usb_ram_packet_out + 1 ;
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end
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else
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usb_ram_offset_out <= usb_ram_offset_out + 1 ;
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end
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if (usb_ram_ain == usb_ram_aout)
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isfull <= 0;
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end
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/* RAM Reading Process */
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always @(posedge clock)
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begin
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ram_data_out <= usb_ram[usb_ram_aout] ;
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end
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endmodule
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