mirror of https://gerrit.osmocom.org/libusrp
707f3cef77
* Public USRP(1) header files are now in their own source directory and install into $(includedir)/usrp. This was done to avoid name clashes in the top-level include directory. Only users who are developing directly to libusrp in C++ are affected; the GNU Radio C++ and Python APIs are unchanged. The simple change required by this update is to change: #include <usrp_*.h> to #include <usrp/usrp_*.h> ...in your source code. * Removed usrp-inband code from tree (put into limbo directory.) This code has become unmaintained and has started to suffer from bitrot. A checkpoint tag has been made for anyone still needing to use it: http://gnuradio.org/svn/gnuradio/tags/checkpoints/trunk-20090708-pre-usrp-reorg The plan during the 3.2->3.3 development cycle is to replace the functions done by the in-band code with extensions to the existing gr-usrp blocks using the new message passing architecture. The USRP hardware FPGA code that provided the inband interface has not been removed; however, it too has become unmaintained and will likely be rewritten/replaced during the 3.3 timeframe. The trunk passes distcheck. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11394 221aa14e-8319-0410-a670-987f0aec2ac5 |
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| doc | ||
| firmware | ||
| fpga | ||
| host | ||
| limbo | ||
| Makefile.am | ||
| README | ||
| usrp.inf | ||
| usrp.iss.in | ||
| usrp.pc.in | ||
README
# # README -- the short version # The top level makefile handles the host code and FX2 firmware. Besides the normal gcc suite and all the auto tools, you'll need the SDCC free C compiler to build the firmware. You MUST USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable initialization. http://sdcc.sourceforge.net The high level interface to the USRP using our standard FPGA bitstram is contained in usrp/host/lib/usrp_standard.h If you've got doxygen installed, there are html docs in usrp/doc/html/index.html # Compiling the verilog (not required unless you're modifying it) If you want to build the FPGA .rbf file from source (not required; we provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll need Altera's no cost Quartus II development tools. We're currently building with Quartus II 5.1sp1 Web Edition. The project file is usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog modules are contained in usrp/fpga/sdr_lib