mirror of https://gerrit.osmocom.org/libusrp
301 lines
12 KiB
C++
301 lines
12 KiB
C++
/* -*- c++ -*- */
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/*
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* Copyright 2003,2004,2006 Free Software Foundation, Inc.
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*
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* This file is part of GNU Radio
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*
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* GNU Radio is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* GNU Radio is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef INCLUDED_FPGA_REGS_STANDARD_H
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#define INCLUDED_FPGA_REGS_STANDARD_H
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// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
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// Registers 64 to 79 are available for custom FPGA builds.
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// DDC / DUC
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#define FR_INTERP_RATE 32 // [1,1024]
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#define FR_DECIM_RATE 33 // [1,256]
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// DDC center freq
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#define FR_RX_FREQ_0 34
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#define FR_RX_FREQ_1 35
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#define FR_RX_FREQ_2 36
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#define FR_RX_FREQ_3 37
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// See below for DDC Starting Phase
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// ------------------------------------------------------------------------
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// configure FPGA Rx mux
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-----------------------+-------+-------+-------+-------+-+-----+
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// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
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// +-----------------------+-------+-------+-------+-------+-+-----+
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//
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// There are a maximum of 4 digital downconverters in the the FPGA.
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// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
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//
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// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
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//
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// 0 = DDC input is from ADC 0
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// 1 = DDC input is from ADC 1
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// 2 = DDC input is from ADC 2
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// 3 = DDC input is from ADC 3
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//
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// If Z == 1, all DDC Q inputs are set to zero
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// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
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//
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// NCH specifies the number of complex channels that are sent across
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// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
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// 8 16-bit values.
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#define FR_RX_MUX 38
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// ------------------------------------------------------------------------
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// configure FPGA Tx Mux.
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-----------------------+-------+-------+-------+-------+-+-----+
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// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
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// +-----------------------------------------------+-------+-+-----+
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//
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// NCH specifies the number of complex channels that are sent across
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// the USB. The legal values are 1 or 2, corresponding to 2 or 4
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// 16-bit values.
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//
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// There are two interpolators with complex inputs and outputs.
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// There are four DACs. (We use the DUC in each AD9862.)
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//
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// Each 4-bit DACx field specifies the source for the DAC and
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// whether or not that DAC is enabled. Each subfield is coded
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// like this:
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//
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// 3 2 1 0
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// +-+-----+
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// |E| N |
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// +-+-----+
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//
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// Where E is set if the DAC is enabled, and N specifies which
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// interpolator output is connected to this DAC.
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//
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// N which interp output
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// --- -------------------
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// 0 chan 0 I
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// 1 chan 0 Q
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// 2 chan 1 I
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// 3 chan 1 Q
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#define FR_TX_MUX 39
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// ------------------------------------------------------------------------
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// REFCLK control
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//
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// Control whether a reference clock is sent to the daughterboards,
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// and what frequency. The refclk is sent on d'board i/o pin 0.
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-----------------------------------------------+-+------------+
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// | Reserved (Must be zero) |E| DIVISOR |
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// +-----------------------------------------------+-+------------+
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//
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// Bit 7 -- 1 turns on refclk, 0 allows IO use
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// Bits 6:0 Divider value
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#define FR_TX_A_REFCLK 40
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#define FR_RX_A_REFCLK 41
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#define FR_TX_B_REFCLK 42
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#define FR_RX_B_REFCLK 43
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# define bmFR_REFCLK_EN 0x80
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# define bmFR_REFCLK_DIVISOR_MASK 0x7f
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// ------------------------------------------------------------------------
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// DDC Starting Phase
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#define FR_RX_PHASE_0 44
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#define FR_RX_PHASE_1 45
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#define FR_RX_PHASE_2 46
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#define FR_RX_PHASE_3 47
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// ------------------------------------------------------------------------
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// Tx data format control register
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-------------------------------------------------------+-------+
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// | Reserved (Must be zero) | FMT |
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// +-------------------------------------------------------+-------+
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//
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// FMT values:
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#define FR_TX_FORMAT 48
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# define bmFR_TX_FORMAT_16_IQ 0 // 16-bit I, 16-bit Q
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// ------------------------------------------------------------------------
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// Rx data format control register
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-----------------------------------------+-+-+---------+-------+
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// | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
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// +-----------------------------------------+-+-+---------+-------+
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//
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// FMT values:
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#define FR_RX_FORMAT 49
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# define bmFR_RX_FORMAT_SHIFT_MASK (0x0f << 0) // arithmetic right shift [0, 15]
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# define bmFR_RX_FORMAT_SHIFT_SHIFT 0
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# define bmFR_RX_FORMAT_WIDTH_MASK (0x1f << 4) // data width in bits [1, 16] (not all valid)
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# define bmFR_RX_FORMAT_WIDTH_SHIFT 4
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# define bmFR_RX_FORMAT_WANT_Q (0x1 << 9) // deliver both I & Q, else just I
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# define bmFR_RX_FORMAT_BYPASS_HB (0x1 << 10) // bypass half-band filter
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// The valid combinations currently are:
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//
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// B Q WIDTH SHIFT
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// 0 1 16 0
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// 0 1 8 8
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// Possible future values of WIDTH = {4, 2, 1}
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// 12 takes a bit more work, since we need to know packet alignment.
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// ------------------------------------------------------------------------
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// FIXME register numbers 50 to 63 are available
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// ------------------------------------------------------------------------
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// Registers 64 to 95 are reserved for user custom FPGA builds.
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// The standard USRP software will not touch these.
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#define FR_USER_0 64
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#define FR_USER_1 65
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#define FR_USER_2 66
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#define FR_USER_3 67
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#define FR_USER_4 68
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#define FR_USER_5 69
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#define FR_USER_6 70
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#define FR_USER_7 71
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#define FR_USER_8 72
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#define FR_USER_9 73
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#define FR_USER_10 74
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#define FR_USER_11 75
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#define FR_USER_12 76
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#define FR_USER_13 77
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#define FR_USER_14 78
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#define FR_USER_15 79
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#define FR_USER_16 80
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#define FR_USER_17 81
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#define FR_USER_18 82
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#define FR_USER_19 83
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#define FR_USER_20 84
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#define FR_USER_21 85
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#define FR_USER_22 86
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#define FR_USER_23 87
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#define FR_USER_24 88
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#define FR_USER_25 89
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#define FR_USER_26 90
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#define FR_USER_27 91
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#define FR_USER_28 92
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#define FR_USER_29 93
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#define FR_USER_30 94
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#define FR_USER_31 95
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//Registers needed for multi usrp master/slave configuration
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//
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//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
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//
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#define FR_RX_MASTER_SLAVE 64
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#define bitnoFR_RX_SYNC 0
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#define bitnoFR_RX_SYNC_MASTER 1
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#define bitnoFR_RX_SYNC_SLAVE 2
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# define bmFR_RX_SYNC (1 <<bitnoFR_RX_SYNC) //1 If this is a master "sync now" and send sync to slave.
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// If this is a slave "sync now" (testing purpose only)
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// Sync is allmost the same as reset (clear all counters and buffers)
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// except that the io outputs and settings don't get reset (otherwise it couldn't send the sync to the slave)
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//0 Normal operation
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# define bmFR_RX_SYNC_MASTER (1 <<bitnoFR_RX_SYNC_MASTER) //1 This is a rx sync master, output sync_rx on rx_a_io[15]
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//0 This is not a rx sync master
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# define bmFR_RX_SYNC_SLAVE (1 <<bitnoFR_RX_SYNC_SLAVE) //1 This is a rx sync slave, follow sync_rx on rx_a_io[bitnoFR_RX_SYNC_INPUT_IOPIN]
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//0 This is not an rx sync slave.
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//Caution The master settings will output values on the io lines.
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//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
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//If you set the slave bits then your usrp won't do anything if you don't connect a master.
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// Rx Master/slave control register
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//
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// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
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// This can be done with basic_rx boards or dbsrx boards
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//dbsrx: connect master-J25 to slave-J25
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//basic rx: connect J25 to slave-J25
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//CAUTION: pay attention to the lineup of your connector.
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//The red line (pin1) should be at the same side of the daughterboards on master and slave.
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//If you turnaround the cable on one end you will burn your usrp.
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//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
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//You can still link them but you must use only a 2pin or 1pin cable
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//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
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//You can use a cable like the ones found with the leds on the mainbord of a PC.
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//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
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//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
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// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
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// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
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// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
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#define bitnoFR_RX_SYNC_INPUT_IOPIN 15
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#define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
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//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
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#define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
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#define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
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// =======================================================================
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// READBACK Registers
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// =======================================================================
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#define FR_RB_IO_RX_A_IO_TX_A 1 // read back a-side i/o pins
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#define FR_RB_IO_RX_B_IO_TX_B 2 // read back b-side i/o pins
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// ------------------------------------------------------------------------
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// FPGA Capability register
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-----------------------------------------------+-+-----+-+-----+
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// | Reserved (Must be zero) |T|NDUC |R|NDDC |
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// +-----------------------------------------------+-+-----+-+-----+
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//
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// Bottom 4-bits are Rx capabilities
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// Next 4-bits are Tx capabilities
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#define FR_RB_CAPS 3
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# define bmFR_RB_CAPS_NDDC_MASK (0x7 << 0) // # of digital down converters 0,1,2,4
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# define bmFR_RB_CAPS_NDDC_SHIFT 0
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# define bmFR_RB_CAPS_RX_HAS_HALFBAND (0x1 << 3)
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# define bmFR_RB_CAPS_NDUC_MASK (0x7 << 4) // # of digital up converters 0,1,2
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# define bmFR_RB_CAPS_NDUC_SHIFT 4
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# define bmFR_RB_CAPS_TX_HAS_HALFBAND (0x1 << 7)
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#endif /* INCLUDED_FPGA_REGS_STANDARD_H */
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