mirror of https://gerrit.osmocom.org/libusrp
151 lines
5.0 KiB
C++
151 lines
5.0 KiB
C++
/* -*- c++ -*- */
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/*
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* Copyright 2003,2004 Free Software Foundation, Inc.
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*
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* This file is part of GNU Radio
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*
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* GNU Radio is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* GNU Radio is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef INCLUDED_FPGA_REGS_COMMON_H
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#define INCLUDED_FPGA_REGS_COMMON_H
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// This file defines registers common to all FPGA configurations.
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// Registers 0 to 31 are reserved for use in this file.
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// The FPGA needs to know the rate that samples are coming from and
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// going to the A/D's and D/A's. div = 128e6 / sample_rate
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#define FR_TX_SAMPLE_RATE_DIV 0
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#define FR_RX_SAMPLE_RATE_DIV 1
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// 2 and 3 are defined in the ATR section
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#define FR_MASTER_CTRL 4 // master enable and reset controls
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# define bmFR_MC_ENABLE_TX (1 << 0)
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# define bmFR_MC_ENABLE_RX (1 << 1)
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# define bmFR_MC_RESET_TX (1 << 2)
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# define bmFR_MC_RESET_RX (1 << 3)
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// i/o direction registers for pins that go to daughterboards.
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// Setting the bit makes it an output from the FPGA to the d'board.
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// top 16 is mask, low 16 is value
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#define FR_OE_0 5 // slot 0
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#define FR_OE_1 6
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#define FR_OE_2 7
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#define FR_OE_3 8
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// i/o registers for pins that go to daughterboards.
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// top 16 is a mask, low 16 is value
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#define FR_IO_0 9 // slot 0
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#define FR_IO_1 10
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#define FR_IO_2 11
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#define FR_IO_3 12
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#define FR_MODE 13
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# define bmFR_MODE_NORMAL 0
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# define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback
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# define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting
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# define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter
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// low and high 16 bits are multiplexed across channel I and Q
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// If the corresponding bit is set, internal FPGA debug circuitry
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// controls the i/o pins for the associated bank of daughterboard
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// i/o pins. Typically used for debugging FPGA designs.
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#define FR_DEBUG_EN 14
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# define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
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# define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
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# define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
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# define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
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// If the corresponding bit is set, enable the automatic DC
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// offset correction control loop.
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//
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// The 4 low bits are significant:
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//
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// ADC0 = (1 << 0)
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// ADC1 = (1 << 1)
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// ADC2 = (1 << 2)
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// ADC3 = (1 << 3)
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//
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// This control loop works if the attached daugherboard blocks DC.
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// Currently all daughterboards do block DC. This includes:
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// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
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#define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable
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// offset corrections for ADC's and DAC's (2's complement)
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#define FR_ADC_OFFSET_0 16
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#define FR_ADC_OFFSET_1 17
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#define FR_ADC_OFFSET_2 18
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#define FR_ADC_OFFSET_3 19
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// ------------------------------------------------------------------------
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// Automatic Transmit/Receive switching
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//
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// If automatic transmit/receive (ATR) switching is enabled in the
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// FR_ATR_CTL register, the presence or absence of data in the FPGA
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// transmit fifo selects between two sets of values for each of the 4
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// banks of daughterboard i/o pins.
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//
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// Each daughterboard slot has 3 16-bit registers associated with it:
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// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
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//
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// FR_ATR_MASK_{0,1,2,3}:
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//
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// These registers determine which of the daugherboard i/o pins are
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// affected by ATR switching. If a bit in the mask is set, the
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// corresponding i/o bit is controlled by ATR, else it's output
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// value comes from the normal i/o pin output register:
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// FR_IO_{0,1,2,3}.
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//
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// FR_ATR_TXVAL_{0,1,2,3}:
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// FR_ATR_RXVAL_{0,1,2,3}:
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//
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// If the Tx fifo contains data, then the bits from TXVAL that are
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// selected by MASK are output. Otherwise, the bits from RXVAL that
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// are selected by MASK are output.
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#define FR_ATR_MASK_0 20 // slot 0
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#define FR_ATR_TXVAL_0 21
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#define FR_ATR_RXVAL_0 22
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#define FR_ATR_MASK_1 23 // slot 1
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#define FR_ATR_TXVAL_1 24
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#define FR_ATR_RXVAL_1 25
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#define FR_ATR_MASK_2 26 // slot 2
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#define FR_ATR_TXVAL_2 27
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#define FR_ATR_RXVAL_2 28
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#define FR_ATR_MASK_3 29 // slot 3
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#define FR_ATR_TXVAL_3 30
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#define FR_ATR_RXVAL_3 31
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// Clock ticks to delay rising and falling edge of T/R signal
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#define FR_ATR_TX_DELAY 2
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#define FR_ATR_RX_DELAY 3
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#endif /* INCLUDED_FPGA_REGS_COMMON_H */
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