mirror of https://gerrit.osmocom.org/libusrp
400 lines
16 KiB
XML
400 lines
16 KiB
XML
<?xml version="1.0" encoding="ISO-8859-1"?>
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<!DOCTYPE article PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN"
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"docbookx.dtd" [
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]>
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<article>
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<articleinfo>
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<title>USRP User's and Developer's Guide</title>
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<author>
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<firstname>Matt</firstname>
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<surname>Ettus</surname>
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<affiliation>
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<orgname>Ettus Research LLC</orgname>
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<address>
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Ettus Research LLC
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<street>604 Mariposa Ave</street>
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<city>Mountain View</city>, <state>CA</state> <postcode>94041</postcode>
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<country>USA</country>
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<email>matt@ettus.com</email>
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</address>
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</affiliation>
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</author>
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<abstract>
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<para>
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This guide explains both basic usage of the USRP as well as how to expand it.
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</para>
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</abstract>
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</articleinfo>
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<sect1 id="intro">
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<title>Introduction</title>
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<para>
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The Universal Software Radio Peripheral, or USRP (pronounced "usurp")
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is designed to allow general purpose computers to function as high
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bandwidth software radios. In essence, it serves as a digital
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baseband and IF section of a radio communication system. In addition,
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it has a well-defined electrical and mechanical interface to RF
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front-ends (daughterboards) which can translate between that IF or
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baseband and the RF bands of interest
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</para>
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<para>
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The basic design philosophy behind the USRP has been to do all of the
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waveform-specific processing, like modulation and demodulation, on the
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host CPU. All of the high-speed general purpose operations like
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digital up- and downconversion, decimation and interpolation are done
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on the FPGA.
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</para>
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<para>
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It is anticipated that the majority of USRP users will never need to
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use anything other than the standard FPGA configuration. However, for
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those users that wish to, the FPGA design may be changed or replaced.
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All of the interfaces are well defined and documented.
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</para>
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<figure id="usrp-board">
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<title>USRP with Daughterboards</title>
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<mediaobject>
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<imageobject><imagedata fileref="usrp.jpg" format="JPG"/></imageobject>
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<caption><para>
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This USRP has 2 BasicTX and 2 BasicRX boards mounted on it.
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Notice that the boards on the left are rotated 180 degrees.
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</para></caption>
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</mediaobject>
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</figure>
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<sect2 id="requirements">
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<title>System Requirements</title>
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<para>
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The USRP requires a PC or Mac with a USB2 interface.
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</para>
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</sect2>
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<sect2 id="capabilities">
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<title>Capabilities</title>
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<para>
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The USRP has 4 high-speed analog to digital converters (ADCs), each at
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12 bits per sample, 64 million samples per second. There are also
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4 high-speed digital to analog converters (DACs), each at 14 bits per
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sample, 128 million samples per second. These 4 input and 4 output
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channels are connected to an Altera Cyclone EP1C12 FPGA. The FPGA, in
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turn, connects to a USB2 interface chip, the Cypress FX2, and on to the
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computer. The USRP connects to the computer via a high speed USB2
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interface only, and will not work with USB1.1.
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</para>
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<figure id="usrp-block-diagram-fig"><title>Universal Software Radio Peripheral</title>
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<mediaobject>
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<imageobject><imagedata fileref="usrp-block-diagram.eps" format="EPS"/></imageobject>
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<imageobject><imagedata fileref="usrp-block-diagram.png" format="PNG"/></imageobject>
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<caption><para></para></caption>
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</mediaobject>
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</figure>
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</sect2>
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</sect1>
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<sect1 id="getting-started">
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<title>Getting Started</title>
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<sect2 id="the-code">
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<title>Getting all the Software</title>
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<para>
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The first step in using your USRP system is to get all of GNU Radio installed. This can
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sometimes be a daunting process, as there are several other libraries which will need to be
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installed first.
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</para>
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<sect3 id="dependencies">
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<title>Library Dependencies</title>
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<itemizedlist>
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<listitem>
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<para>SWIG</para>
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<para>
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We use SWIG (Simple Wrapper Interface Generator) to tie together the C++ and Python code
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in the GNU Radio system. We require that you have version 1.3.24 or newer. You'll
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probably have to compile it from source, which you can find here: <ulink url="http://www.swig.org">SWIG</ulink>
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</para>
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</listitem>
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<listitem>
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<para>FFTW</para>
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<para>
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FFTW is the library which GNU Radio uses for FFTs. GNU Radio requires version 3.0.1 or
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newer, and it must be compiled for single precision. You can get it from the
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<ulink url="http://www.fftw.org">FFTW Homepage</ulink>
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</para>
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</listitem>
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<listitem>
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<para>Boost Library</para>
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<para>
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Boost provides several low-level structures used in our C++ code. If it is not included in
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your OS distribution, you can get it here: <ulink url="http://boost.org">Boost</ulink>
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</para>
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</listitem>
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<listitem>
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<para>CPP Unit</para>
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<para>
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CPPUnit provides our unit-testing framework. This creates automated tests to insure that
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code does not break when changes are made. Get it at the <ulink url="http://cppunit.sf.net">
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CPP Unit Homepage</ulink>
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</para>
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</listitem>
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</itemizedlist>
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</sect3>
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<sect3 id="getting-gradio">
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<title>Getting GNU Radio and the USRP code</title>
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<para>
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There are several packages of software which make up GNU Radio and the USRP support software.
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Links to the latest versions of each can be found on the GNU Radio Wiki at
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<ulink url="http://comsec.com/wiki?GnuRadio2.X">Download Links</ulink>. Gr-build
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can greatly simplify the installation process, and its use it highly recommended.
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</para>
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</sect3>
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<sect3 id="cvs">
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<title>Following CVS Development</title>
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<para>
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Development for the USRP proceeds very quickly at times, so some users may want to keep up with
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the latest by following the CVS trees. There are three separate software repositories
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which contain various parts of the USRP system.
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<itemizedlist>
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<listitem>
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<para>
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USRP-HW, containing the hardware and FPGA designs.
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</para>
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<para>
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All of the schematics in this repository were created in
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<ulink url="http://www.geda.seul.org">gEDA</ulink>. The board
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layouts were created in <ulink url="http://pcb.sf.net">PCB</ulink>.
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Verilog designs are compiled in Quartus II Web Edition from
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<ulink url="http://www.altera.com">Altera</ulink>.
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</para>
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</listitem>
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<listitem>
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<para>
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<ulink url="https://sourceforge.net/cvs/?group_id=22397">USRP-SW</ulink>,
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USRP-SW, containing firmware and host drivers for the USRP
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</para>
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<para>
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Host side drivers and firmware which runs in the USB2 interface chip on the board.
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</para>
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</listitem>
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<listitem>
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<para>
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<ulink url="http://comsec.com/wiki?CvsAccess">GNU Radio/gr-usrp</ulink>
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which contains the GNU Radio interface to the USRP
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</para>
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</listitem>
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</itemizedlist>
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</para>
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</sect3>
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</sect2>
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<sect2 id="usrp-start">
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<title>Using your USRP</title>
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<sect3 id="physical">
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<title>Mechanical Connection</title>
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<para>
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The USRP ships with a complete set of standoffs, nuts and bolts. There are 20 standoffs,
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M3x10mm M-F, of which 4 are intended to be used as "feet" for the USRP. Place them in the 4
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corner holes on the main board, inserting the male part from below. The remaining 16
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are used to hold the daughterboards in place. Four of them should be connected to the male
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portion of the 4 standoffs already inserted from below. The remaining 12 should be
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connected to the board with the 12 M3x6mm screws from below. At this point there should be
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16 standoffs on the board with the male ends up to serve as a guide for the daughterboards.
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The 16 M3 nuts are used to fasten the daughterboards down to the main board.
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</para>
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<para>
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The USRP accomodates 2 TX and 2 RX daughterboards. The placement of the standoffs is designed
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to prevent the accidental incorrect connection of daughterboards. The 2 sides of the USRP have
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their daughterboard slots rotated 180 degrees. The USRP should not be operated without
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standoffs, and daughterboards should never be connected or removed while power is applied.
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</para>
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</sect3>
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<sect3 id="electrical">
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<title>Electrical Connections</title>
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<para>
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The USRP is powered by a 6V 4A power converter included in the kit. The converter is
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capable of 90-260 Vac, 50/60 Hz operation, and so should work in any country.
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If there is a need to use another power supply, the connector is a standard 2.1mm/5.5mm
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DC power connector. The USRP itself only needs 5V at 2A, but a 6V supply was chosen to
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accomodate future daughterboards. Extra power supplies are available from Ettus Research.
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</para>
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<para>
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The included USB cable should be connected to a USB2-capable socket on a computer. The USRP
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does not support USB 1.1 operation at this time.
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</para>
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</sect3>
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<sect3 id="diagnostics">
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<title>Troubleshooting</title>
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<para>
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When first powered up, an LED on the USRP should be flashing at about 3-4x per second.
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This indicates that the processor is running, and has put the device in a low power mode.
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Once firmware has been downloaded to the USRP, the LED will blink at a slower rate.
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If there is no blinking LED, check all power connections, and check for continuity
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in the power fuse (F501, near the power connector). If the fuse needs replacement, it
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is size 0603, 3 amps.
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</para>
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</sect3>
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</sect2>
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</sect1>
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<sect1 id="fpga">
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<title>FPGA</title>
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<sect2 id="fpga-std">
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<title>Standard FPGA Configuration</title>
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<para>
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In the standard fpga configuration, usrp_std, all samples sent over
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the USB interface are in 16-bit signed integers in IQ format. When
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there are multiple channels (up to 4), the channels are interleaved.
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For example, with 4 channels, the sequence would be I0 Q0 I1 Q1 I2 Q2
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I3 Q3 I0 Q0, etc.
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</para>
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<para>
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The USRP can operate in full duplex mode. When in this mode, the
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transmit and receive sides are completely independent of one another.
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The only consideration is that the combined data rate over the bus
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must be 32 Megabytes per second or less. The multiple RX channels
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(1,2, or 4) must all be the same data rate (i.e. same decimation
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ratio). The same applies to the 1,2, or TX channels, which each must
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be at the same data rate (which may be different from the RX rate).
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</para>
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<para>
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On the RX side, each of the 4 ADCs can be routed to either of I or the
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Q input of any of the 4 downconverters. This allows for having
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multiple channels selected out of the same ADC sample stream.
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</para>
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<para>
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The digital upconverters (DUCs) on the transmit side are actually
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contained in the AD9862 CODEC chips, not in the FPGA. The only
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transmit signal processing blocks in the FPGA are the interpolators.
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The interpolator outputs can be routed to any of the 4 CODEC inputs.
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</para>
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<figure id="ddc-fig"><title>Digital Down Converter Block Diagram</title>
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<mediaobject>
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<imageobject><imagedata fileref="ddc.eps" format="EPS"/></imageobject>
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<imageobject><imagedata fileref="ddc.png" format="PNG"/></imageobject>
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<caption><para></para></caption>
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</mediaobject>
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</figure>
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</sect2>
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</sect1>
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<sect1 id="dboard-int">
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<title>Daughterboard Interface</title>
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<sect2 id="power-int">
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<title>Power</title>
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<para>
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Daughterboards are provided with clean regulated 3.3V for the analog
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and digital sections. Additionally there is a 6V connection straight from
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the wall supply which is intended to supply a 5V LDO regulator. All daughterboards
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may draw a combined total of 1.5 A.
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</para>
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</sect2>
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<sect2 id="logical-int">
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<title>Logical Interface</title>
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<para>
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There are slots for 2 TX daughterboards, labeled TXA and TXB, and 2
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corresponding RX daughterboards, RXA and RXB. Each daughterboard slot has
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access to 2 of the 4 high-speed data converter analog signals (DAC outputs
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for TX, ADC inputs for RX). This allows each daughterboard which uses real
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(not IQ) sampling to have 2 independent RF sections, and 2 antennas
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(4 total for the system). If IQ sampling is used, each board can support
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a single RF section, for a total of 2 for the whole system.
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</para>
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<para>
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No antialias or reconstruction filtering is provided on the USRP motherboard.
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This allows for maximum flexibility in frequency planning for the
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daughterboards. The analog input bandwidth of the ADCs is over 200 MHz, so
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IF frequencies up to that high may be chosen. If several decibels of loss
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is tolerable, and IF frequency as high as 500 MHz can be used.
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</para>
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<para>
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Every daughterboard has an I2C EEPROM (24LC024 or 24LC025) onboard
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which identifies the board to the system. This allows the host
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software to automatically set up the system properly based on the
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installed daughterboard. The EEPROM may also store calibration values
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like DC offsets or IQ imbalances. If this EEPROM is not programmed, a
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warning message is printed every time USRP software is run.
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</para>
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</sect2>
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<sect2 id="analog-int">
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<title>Analog Interface</title>
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<para>
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Each RX daughterboard has 2 differential analog inputs
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(VINP_A/VINN_A and VINP_B/VINN_B) which are sampled at a rate of 64 MS/s.
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The input impedance is approximately 1Kohm.
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The motherboard has a software-controllable programmable gain amplifier
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on these inputs, with 0 to 20 dB of gain. With gain set to zero, full
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scale inputs are 2 Volts peak-to-peak differential. When set to 20 dB,
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only .2 V pk-pk differential is needed to reach full scale.
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</para>
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<para>
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If signals are AC-coupled, there is no need to provide DC bias as long as the
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internal buffer is turned on. It will provide an approximately 2V bias.
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If signals are DC-couple, a DC bias of Vdd/2 (1.65V) should be provided to
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both the positive and negative inputs, and the internal buffer should be turned off.
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VREF provides a clean 1 V reference.
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</para>
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<para>
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Each TX daughterboard has a pair of differential analog outputs which are
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updated at 128 MS/s. The signals (IOUTP_A/IOUTN_A and IOUTP_B/IOUTN_B) are
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current-output, each varying between 0 and 20 mA. Since they are high-impedance,
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they can be converted into differential voltages with a resistor.
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</para>
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<para>
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In addition to the high-speed signals, each daughterboard has exclusive access to 2 low-speed ADC inputs
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(labeled AUX_ADC_A and AUX_ADC_B) which can be read from software.
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These are useful for sensing RSSI signal levels, temperatures, bias
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levels, etc. Additionally, each board has shared access to 4 low-speed DAC
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signals, labeled AUX_DAC_A through AUX_DAC_D. RXA and TXA share one set
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of these 4 lines, and RXB and TXB share their own independent set. These
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signals are useful for controlling gain of variable-gain amplifiers, for example.
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AUX_ADC_REF provides a reference level for gain setting if it is necessary.
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</para>
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</sect2>
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<sect2 id="dig-int">
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<title>Digital Interface</title>
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<para></para>
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</sect2>
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<sect2 id="mech-int">
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<title>Connector Pinouts</title>
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<table frame='all'><title>RX DBoard Connector</title>
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<tgroup cols='3' align='left' colsep='1' rowsep='1'>
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<thead>
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<row>
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<entry>Pin #</entry>
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<entry>Name</entry>
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<entry>Description</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry>1</entry>
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<entry>power</entry>
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<entry>This is power</entry>
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</row>
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<row>
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<entry>c1</entry>
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<entry>c4</entry>
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</row>
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<row>
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<entry>d1</entry>
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<entry>d4</entry>
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<entry>d5</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</sect2>
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</sect1>
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<sect1 id="dboards">
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<title>Available Daughterboards</title>
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<sect2 id="basicrx">
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<title>BasicRX</title>
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<para>
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</para>
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</sect2>
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<sect2 id="basictx">
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<title>BasicTX</title>
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<para>
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</para>
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</sect2>
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</sect1>
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</article>
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