mirror of https://gerrit.osmocom.org/libusrp
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories.
This commit is contained in:
Johnathan Corgan
parent
acd46373d4
commit
dc8d1a4973
|
|
@ -20,5 +20,3 @@
|
|||
#
|
||||
|
||||
SUBDIRS = rbf
|
||||
|
||||
include Makefile.extra
|
||||
|
|
|
|||
|
|
@ -1,181 +0,0 @@
|
|||
EXTRA_DIST = \
|
||||
gen_makefile_extra.py \
|
||||
inband_lib/chan_fifo_reader.v \
|
||||
inband_lib/channel_demux.v \
|
||||
inband_lib/channel_ram.v \
|
||||
inband_lib/cmd_reader.v \
|
||||
inband_lib/packet_builder.v \
|
||||
inband_lib/register_io.v \
|
||||
inband_lib/rx_buffer_inband.v \
|
||||
inband_lib/tx_buffer_inband.v \
|
||||
inband_lib/tx_packer.v \
|
||||
inband_lib/usb_packet_fifo.v \
|
||||
megacells/accum32.bsf \
|
||||
megacells/accum32.cmp \
|
||||
megacells/accum32.inc \
|
||||
megacells/accum32.v \
|
||||
megacells/accum32_bb.v \
|
||||
megacells/accum32_inst.v \
|
||||
megacells/add32.bsf \
|
||||
megacells/add32.cmp \
|
||||
megacells/add32.inc \
|
||||
megacells/add32.v \
|
||||
megacells/add32_bb.v \
|
||||
megacells/add32_inst.v \
|
||||
megacells/addsub16.bsf \
|
||||
megacells/addsub16.cmp \
|
||||
megacells/addsub16.inc \
|
||||
megacells/addsub16.v \
|
||||
megacells/addsub16_bb.v \
|
||||
megacells/addsub16_inst.v \
|
||||
megacells/bustri.bsf \
|
||||
megacells/bustri.cmp \
|
||||
megacells/bustri.inc \
|
||||
megacells/bustri.v \
|
||||
megacells/bustri_bb.v \
|
||||
megacells/bustri_inst.v \
|
||||
megacells/clk_doubler.v \
|
||||
megacells/clk_doubler_bb.v \
|
||||
megacells/dspclkpll.v \
|
||||
megacells/dspclkpll_bb.v \
|
||||
megacells/fifo_1kx16.bsf \
|
||||
megacells/fifo_1kx16.cmp \
|
||||
megacells/fifo_1kx16.inc \
|
||||
megacells/fifo_1kx16.v \
|
||||
megacells/fifo_1kx16_bb.v \
|
||||
megacells/fifo_1kx16_inst.v \
|
||||
megacells/fifo_2k.v \
|
||||
megacells/fifo_2k_bb.v \
|
||||
megacells/fifo_4k.v \
|
||||
megacells/fifo_4k_18.v \
|
||||
megacells/fifo_4k_bb.v \
|
||||
megacells/fifo_4kx16_dc.bsf \
|
||||
megacells/fifo_4kx16_dc.cmp \
|
||||
megacells/fifo_4kx16_dc.inc \
|
||||
megacells/fifo_4kx16_dc.v \
|
||||
megacells/fifo_4kx16_dc_bb.v \
|
||||
megacells/fifo_4kx16_dc_inst.v \
|
||||
megacells/mylpm_addsub.bsf \
|
||||
megacells/mylpm_addsub.cmp \
|
||||
megacells/mylpm_addsub.inc \
|
||||
megacells/mylpm_addsub.v \
|
||||
megacells/mylpm_addsub_bb.v \
|
||||
megacells/mylpm_addsub_inst.v \
|
||||
megacells/pll.v \
|
||||
megacells/pll_bb.v \
|
||||
megacells/pll_inst.v \
|
||||
megacells/sub32.bsf \
|
||||
megacells/sub32.cmp \
|
||||
megacells/sub32.inc \
|
||||
megacells/sub32.v \
|
||||
megacells/sub32_bb.v \
|
||||
megacells/sub32_inst.v \
|
||||
models/bustri.v \
|
||||
models/fifo.v \
|
||||
models/fifo_1c_1k.v \
|
||||
models/fifo_1c_2k.v \
|
||||
models/fifo_1c_4k.v \
|
||||
models/fifo_1k.v \
|
||||
models/fifo_2k.v \
|
||||
models/fifo_4k.v \
|
||||
models/fifo_4k_18.v \
|
||||
models/pll.v \
|
||||
models/ssram.v \
|
||||
sdr_lib/adc_interface.v \
|
||||
sdr_lib/atr_delay.v \
|
||||
sdr_lib/bidir_reg.v \
|
||||
sdr_lib/cic_dec_shifter.v \
|
||||
sdr_lib/cic_decim.v \
|
||||
sdr_lib/cic_int_shifter.v \
|
||||
sdr_lib/cic_interp.v \
|
||||
sdr_lib/clk_divider.v \
|
||||
sdr_lib/cordic.v \
|
||||
sdr_lib/cordic_stage.v \
|
||||
sdr_lib/ddc.v \
|
||||
sdr_lib/dpram.v \
|
||||
sdr_lib/duc.v \
|
||||
sdr_lib/ext_fifo.v \
|
||||
sdr_lib/gen_cordic_consts.py \
|
||||
sdr_lib/gen_sync.v \
|
||||
sdr_lib/hb/acc.v \
|
||||
sdr_lib/hb/coeff_rom.v \
|
||||
sdr_lib/hb/halfband_decim.v \
|
||||
sdr_lib/hb/halfband_interp.v \
|
||||
sdr_lib/hb/hbd_tb/test_hbd.v \
|
||||
sdr_lib/hb/mac.v \
|
||||
sdr_lib/hb/mult.v \
|
||||
sdr_lib/hb/ram16_2port.v \
|
||||
sdr_lib/hb/ram16_2sum.v \
|
||||
sdr_lib/hb/ram32_2sum.v \
|
||||
sdr_lib/io_pins.v \
|
||||
sdr_lib/master_control.v \
|
||||
sdr_lib/master_control_multi.v \
|
||||
sdr_lib/phase_acc.v \
|
||||
sdr_lib/ram.v \
|
||||
sdr_lib/ram16.v \
|
||||
sdr_lib/ram32.v \
|
||||
sdr_lib/ram64.v \
|
||||
sdr_lib/rssi.v \
|
||||
sdr_lib/rx_buffer.v \
|
||||
sdr_lib/rx_chain.v \
|
||||
sdr_lib/rx_chain_dual.v \
|
||||
sdr_lib/rx_dcoffset.v \
|
||||
sdr_lib/serial_io.v \
|
||||
sdr_lib/setting_reg.v \
|
||||
sdr_lib/setting_reg_masked.v \
|
||||
sdr_lib/sign_extend.v \
|
||||
sdr_lib/strobe_gen.v \
|
||||
sdr_lib/tx_buffer.v \
|
||||
sdr_lib/tx_chain.v \
|
||||
sdr_lib/tx_chain_hb.v \
|
||||
tb/cbus_tb.v \
|
||||
tb/cordic_tb.v \
|
||||
tb/decim_tb.v \
|
||||
tb/fullchip_tb.v \
|
||||
tb/interp_tb.v \
|
||||
tb/justinterp_tb.v \
|
||||
tb/usrp_tasks.v \
|
||||
toplevel/include/common_config_1rxhb_1tx.vh \
|
||||
toplevel/include/common_config_2rx_0tx.vh \
|
||||
toplevel/include/common_config_2rxhb_0tx.vh \
|
||||
toplevel/include/common_config_2rxhb_2tx.vh \
|
||||
toplevel/include/common_config_4rx_0tx.vh \
|
||||
toplevel/include/common_config_bottom.vh \
|
||||
toplevel/mrfm/biquad_2stage.v \
|
||||
toplevel/mrfm/biquad_6stage.v \
|
||||
toplevel/mrfm/mrfm.csf \
|
||||
toplevel/mrfm/mrfm.esf \
|
||||
toplevel/mrfm/mrfm.psf \
|
||||
toplevel/mrfm/mrfm.py \
|
||||
toplevel/mrfm/mrfm.qpf \
|
||||
toplevel/mrfm/mrfm.qsf \
|
||||
toplevel/mrfm/mrfm.v \
|
||||
toplevel/mrfm/mrfm.vh \
|
||||
toplevel/mrfm/mrfm_compensator.v \
|
||||
toplevel/mrfm/mrfm_fft.py \
|
||||
toplevel/mrfm/mrfm_proc.v \
|
||||
toplevel/mrfm/shifter.v \
|
||||
toplevel/sizetest/sizetest.csf \
|
||||
toplevel/sizetest/sizetest.psf \
|
||||
toplevel/sizetest/sizetest.v \
|
||||
toplevel/usrp_inband_usb/config.vh \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.csf \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.esf \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.psf \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.qpf \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.qsf \
|
||||
toplevel/usrp_inband_usb/usrp_inband_usb.v \
|
||||
toplevel/usrp_multi/config.vh \
|
||||
toplevel/usrp_multi/usrp_multi.csf \
|
||||
toplevel/usrp_multi/usrp_multi.esf \
|
||||
toplevel/usrp_multi/usrp_multi.psf \
|
||||
toplevel/usrp_multi/usrp_multi.qpf \
|
||||
toplevel/usrp_multi/usrp_multi.qsf \
|
||||
toplevel/usrp_multi/usrp_multi.v \
|
||||
toplevel/usrp_std/config.vh \
|
||||
toplevel/usrp_std/usrp_std.csf \
|
||||
toplevel/usrp_std/usrp_std.esf \
|
||||
toplevel/usrp_std/usrp_std.psf \
|
||||
toplevel/usrp_std/usrp_std.qpf \
|
||||
toplevel/usrp_std/usrp_std.qsf \
|
||||
toplevel/usrp_std/usrp_std.v
|
||||
23
fpga/TODO
23
fpga/TODO
|
|
@ -1,23 +0,0 @@
|
|||
|
||||
|
||||
Area Reduction
|
||||
==============
|
||||
Reduce one or both stages of dec/interp to max rate of 8 instead of 16
|
||||
Optimize CICs to minimize registers
|
||||
Reduce width of RX CORDIC
|
||||
Fix CORDIC wasted logic cells from bad synthesis
|
||||
Progressively narrow x,y,z on CORDIC
|
||||
16-bit wide FIFOs, split IQ/channels on other side (?)
|
||||
|
||||
Enhancements
|
||||
============
|
||||
Halfband filter in Spartan 3
|
||||
Muxing of inputs
|
||||
Switch over to newfc
|
||||
RAM interface?
|
||||
|
||||
Other
|
||||
=====
|
||||
Capture/Transmit straight samples (no DUC/DDC)
|
||||
|
||||
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
#!/usr/bin/env python
|
||||
#
|
||||
# Copyright 2006 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of GNU Radio
|
||||
#
|
||||
# GNU Radio is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# GNU Radio is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GNU Radio; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
|
||||
"""
|
||||
Generate Makefile.extra
|
||||
"""
|
||||
|
||||
import sys
|
||||
import os.path
|
||||
|
||||
extensions_we_like = (
|
||||
'.v', '.vh',
|
||||
'.csf', '.esf', '.psf', '.qpf', '.qsf',
|
||||
'.inc', '.cmp', '.bsf',
|
||||
'.py')
|
||||
|
||||
def visit(keepers, dirname, names):
|
||||
if 'rbf' in names:
|
||||
names.remove('rbf')
|
||||
if 'CVS' in names:
|
||||
names.remove('CVS')
|
||||
|
||||
if dirname == '.':
|
||||
dirname = ''
|
||||
if dirname.startswith('./'):
|
||||
dirname = dirname[2:]
|
||||
|
||||
for n in names:
|
||||
base, ext = os.path.splitext(n)
|
||||
if ext in extensions_we_like:
|
||||
keepers.append(os.path.join(dirname, n))
|
||||
|
||||
def generate(f):
|
||||
keepers = []
|
||||
os.path.walk('.', visit, keepers)
|
||||
keepers.sort()
|
||||
write_keepers(keepers, f)
|
||||
|
||||
def write_keepers(files, outf):
|
||||
m = reduce(max, map(len, files), 0)
|
||||
e = 'EXTRA_DIST ='
|
||||
outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' '))
|
||||
for f in files[:-1]:
|
||||
outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' '))
|
||||
outf.write('\t%s\n' % (files[-1],))
|
||||
|
||||
if __name__ == '__main__':
|
||||
generate(open('Makefile.extra','w'))
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
module chan_fifo_reader
|
||||
(reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
|
||||
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
|
||||
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
|
||||
|
||||
input wire reset ;
|
||||
input wire tx_clock ;
|
||||
input wire tx_strobe ; //signal to output tx_i and tx_q
|
||||
input wire [31:0] timestamp_clock ; //current time
|
||||
input wire [3:0] samples_format ;// not useful at this point
|
||||
input wire [31:0] fifodata ; //the data input
|
||||
input wire pkt_waiting ; //signal the next packet is ready
|
||||
output reg rdreq ; //actually an ack to the current fifodata
|
||||
output reg skip ; //finish reading current packet
|
||||
output reg [15:0] tx_q ; //top 16 bit output of fifodata
|
||||
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
|
||||
output reg underrun ;
|
||||
output reg tx_empty ; //cause 0 to be the output
|
||||
input wire [31:0] rssi;
|
||||
input wire [31:0] threshhold;
|
||||
input wire [31:0] rssi_wait;
|
||||
|
||||
output wire [14:0] debug;
|
||||
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
|
||||
|
||||
//Samples format
|
||||
// 16 bits interleaved complex samples
|
||||
`define QI16 4'b0
|
||||
|
||||
// States
|
||||
parameter IDLE = 3'd0;
|
||||
parameter HEADER = 3'd1;
|
||||
parameter TIMESTAMP = 3'd2;
|
||||
parameter WAIT = 3'd3;
|
||||
parameter WAITSTROBE = 3'd4;
|
||||
parameter SEND = 3'd5;
|
||||
|
||||
// Header format
|
||||
`define PAYLOAD 8:2
|
||||
`define ENDOFBURST 27
|
||||
`define STARTOFBURST 28
|
||||
`define RSSI_FLAG 26
|
||||
|
||||
|
||||
/* State registers */
|
||||
reg [2:0] reader_state;
|
||||
/* Local registers */
|
||||
reg [6:0] payload_len;
|
||||
reg [6:0] read_len;
|
||||
reg [31:0] timestamp;
|
||||
reg burst;
|
||||
reg trash;
|
||||
reg rssi_flag;
|
||||
reg [31:0] time_wait;
|
||||
|
||||
always @(posedge tx_clock)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
reader_state <= IDLE;
|
||||
rdreq <= 0;
|
||||
skip <= 0;
|
||||
underrun <= 0;
|
||||
burst <= 0;
|
||||
tx_empty <= 1;
|
||||
tx_q <= 0;
|
||||
tx_i <= 0;
|
||||
trash <= 0;
|
||||
rssi_flag <= 0;
|
||||
time_wait <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case (reader_state)
|
||||
IDLE:
|
||||
begin
|
||||
/*
|
||||
* reset all the variables and wait for a tx_strobe
|
||||
* it is assumed that the ram connected to this fifo_reader
|
||||
* is a short hand fifo meaning that the header to the next packet
|
||||
* is already available to this fifo_reader when pkt_waiting is on
|
||||
*/
|
||||
skip <=0;
|
||||
time_wait <= 0;
|
||||
if (pkt_waiting == 1)
|
||||
begin
|
||||
reader_state <= HEADER;
|
||||
rdreq <= 1;
|
||||
underrun <= 0;
|
||||
end
|
||||
if (burst == 1 && pkt_waiting == 0)
|
||||
underrun <= 1;
|
||||
if (tx_strobe == 1)
|
||||
tx_empty <= 1 ;
|
||||
end
|
||||
|
||||
/* Process header */
|
||||
HEADER:
|
||||
begin
|
||||
if (tx_strobe == 1)
|
||||
tx_empty <= 1 ;
|
||||
|
||||
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
|
||||
//Check Start/End burst flag
|
||||
if (fifodata[`STARTOFBURST] == 1
|
||||
&& fifodata[`ENDOFBURST] == 1)
|
||||
burst <= 0;
|
||||
else if (fifodata[`STARTOFBURST] == 1)
|
||||
burst <= 1;
|
||||
else if (fifodata[`ENDOFBURST] == 1)
|
||||
burst <= 0;
|
||||
|
||||
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
|
||||
begin
|
||||
skip <= 1;
|
||||
reader_state <= IDLE;
|
||||
rdreq <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
payload_len <= fifodata[`PAYLOAD] ;
|
||||
read_len <= 0;
|
||||
rdreq <= 1;
|
||||
reader_state <= TIMESTAMP;
|
||||
end
|
||||
end
|
||||
|
||||
TIMESTAMP:
|
||||
begin
|
||||
timestamp <= fifodata;
|
||||
reader_state <= WAIT;
|
||||
if (tx_strobe == 1)
|
||||
tx_empty <= 1 ;
|
||||
rdreq <= 0;
|
||||
end
|
||||
|
||||
// Decide if we wait, send or discard samples
|
||||
WAIT:
|
||||
begin
|
||||
if (tx_strobe == 1)
|
||||
tx_empty <= 1 ;
|
||||
|
||||
time_wait <= time_wait + 32'd1;
|
||||
// Outdated
|
||||
if ((timestamp < timestamp_clock) ||
|
||||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
|
||||
begin
|
||||
trash <= 1;
|
||||
reader_state <= IDLE;
|
||||
skip <= 1;
|
||||
end
|
||||
// Let's send it
|
||||
else if (timestamp == timestamp_clock
|
||||
|| timestamp == 32'hFFFFFFFF)
|
||||
begin
|
||||
if (rssi <= threshhold || rssi_flag == 0)
|
||||
begin
|
||||
trash <= 0;
|
||||
reader_state <= WAITSTROBE;
|
||||
end
|
||||
else
|
||||
reader_state <= WAIT;
|
||||
end
|
||||
else
|
||||
reader_state <= WAIT;
|
||||
end
|
||||
|
||||
// Wait for the transmit chain to be ready
|
||||
WAITSTROBE:
|
||||
begin
|
||||
// If end of payload...
|
||||
if (read_len == payload_len)
|
||||
begin
|
||||
reader_state <= IDLE;
|
||||
skip <= 1;
|
||||
if (tx_strobe == 1)
|
||||
tx_empty <= 1 ;
|
||||
end
|
||||
else if (tx_strobe == 1)
|
||||
begin
|
||||
reader_state <= SEND;
|
||||
rdreq <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
// Send the samples to the tx_chain
|
||||
SEND:
|
||||
begin
|
||||
reader_state <= WAITSTROBE;
|
||||
read_len <= read_len + 7'd1;
|
||||
tx_empty <= 0;
|
||||
rdreq <= 0;
|
||||
|
||||
case(samples_format)
|
||||
`QI16:
|
||||
begin
|
||||
tx_i <= fifodata[15:0];
|
||||
tx_q <= fifodata[31:16];
|
||||
end
|
||||
|
||||
// Assume 16 bits complex samples by default
|
||||
default:
|
||||
begin
|
||||
tx_i <= fifodata[15:0];
|
||||
tx_q <= fifodata[31:16];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
//error handling
|
||||
reader_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
module channel_demux
|
||||
#(parameter NUM_CHAN = 2) ( //usb Side
|
||||
input [31:0]usbdata_final,
|
||||
input WR_final,
|
||||
// TX Side
|
||||
input reset,
|
||||
input txclk,
|
||||
output reg [NUM_CHAN:0] WR_channel,
|
||||
output reg [31:0] ram_data,
|
||||
output reg [NUM_CHAN:0] WR_done_channel );
|
||||
/* Parse header and forward to ram */
|
||||
|
||||
reg [2:0]reader_state;
|
||||
reg [4:0]channel ;
|
||||
reg [6:0]read_length ;
|
||||
|
||||
// States
|
||||
parameter IDLE = 3'd0;
|
||||
parameter HEADER = 3'd1;
|
||||
parameter WAIT = 3'd2;
|
||||
parameter FORWARD = 3'd3;
|
||||
|
||||
`define CHANNEL 20:16
|
||||
`define PKT_SIZE 127
|
||||
wire [4:0] true_channel;
|
||||
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
|
||||
NUM_CHAN : (usbdata_final[`CHANNEL]);
|
||||
|
||||
always @(posedge txclk)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
reader_state <= IDLE;
|
||||
WR_channel <= 0;
|
||||
WR_done_channel <= 0;
|
||||
end
|
||||
else
|
||||
case (reader_state)
|
||||
IDLE: begin
|
||||
if (WR_final)
|
||||
reader_state <= HEADER;
|
||||
end
|
||||
|
||||
// Store channel and forware header
|
||||
HEADER: begin
|
||||
channel <= true_channel;
|
||||
WR_channel[true_channel] <= 1;
|
||||
ram_data <= usbdata_final;
|
||||
read_length <= 7'd0 ;
|
||||
|
||||
reader_state <= WAIT;
|
||||
end
|
||||
|
||||
WAIT: begin
|
||||
WR_channel[channel] <= 0;
|
||||
|
||||
if (read_length == `PKT_SIZE)
|
||||
reader_state <= IDLE;
|
||||
else if (WR_final)
|
||||
reader_state <= FORWARD;
|
||||
end
|
||||
|
||||
FORWARD: begin
|
||||
WR_channel[channel] <= 1;
|
||||
ram_data <= usbdata_final;
|
||||
read_length <= read_length + 7'd1;
|
||||
|
||||
reader_state <= WAIT;
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
//error handling
|
||||
reader_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
module channel_ram
|
||||
( // System
|
||||
input txclk, input reset,
|
||||
// USB side
|
||||
input [31:0] datain, input WR, input WR_done, output have_space,
|
||||
// Reader side
|
||||
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
|
||||
|
||||
reg [6:0] wr_addr, rd_addr;
|
||||
reg [1:0] which_ram_wr, which_ram_rd;
|
||||
reg [2:0] nb_packets;
|
||||
|
||||
reg [31:0] ram0 [0:127];
|
||||
reg [31:0] ram1 [0:127];
|
||||
reg [31:0] ram2 [0:127];
|
||||
reg [31:0] ram3 [0:127];
|
||||
|
||||
reg [31:0] dataout0;
|
||||
reg [31:0] dataout1;
|
||||
reg [31:0] dataout2;
|
||||
reg [31:0] dataout3;
|
||||
|
||||
wire wr_done_int;
|
||||
wire rd_done_int;
|
||||
wire [6:0] rd_addr_final;
|
||||
wire [1:0] which_ram_rd_final;
|
||||
|
||||
// USB side
|
||||
always @(posedge txclk)
|
||||
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
|
||||
|
||||
always @(posedge txclk)
|
||||
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
|
||||
|
||||
always @(posedge txclk)
|
||||
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
|
||||
|
||||
always @(posedge txclk)
|
||||
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
|
||||
|
||||
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
|
||||
|
||||
always @(posedge txclk)
|
||||
if(reset)
|
||||
wr_addr <= 0;
|
||||
else if (WR_done)
|
||||
wr_addr <= 0;
|
||||
else if (WR)
|
||||
wr_addr <= wr_addr + 7'd1;
|
||||
|
||||
always @(posedge txclk)
|
||||
if(reset)
|
||||
which_ram_wr <= 0;
|
||||
else if (wr_done_int)
|
||||
which_ram_wr <= which_ram_wr + 2'd1;
|
||||
|
||||
assign have_space = (nb_packets < 3'd3);
|
||||
|
||||
// Reader side
|
||||
// short hand fifo
|
||||
// rd_addr_final is what rd_addr is going to be next clock cycle
|
||||
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
|
||||
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
|
||||
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
|
||||
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
|
||||
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
|
||||
|
||||
assign dataout = (which_ram_rd_final[1]) ?
|
||||
(which_ram_rd_final[0] ? dataout3 : dataout2) :
|
||||
(which_ram_rd_final[0] ? dataout1 : dataout0);
|
||||
|
||||
//RD_done is the only way to signal the end of one packet
|
||||
assign rd_done_int = RD_done;
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
rd_addr <= 0;
|
||||
else if (RD_done)
|
||||
rd_addr <= 0;
|
||||
else if (RD)
|
||||
rd_addr <= rd_addr + 7'd1;
|
||||
|
||||
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
|
||||
((RD)?(rd_addr+7'd1):rd_addr);
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
which_ram_rd <= 0;
|
||||
else if (rd_done_int)
|
||||
which_ram_rd <= which_ram_rd + 2'd1;
|
||||
|
||||
assign which_ram_rd_final = (reset) ? (2'd0):
|
||||
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
|
||||
|
||||
//packet_waiting is set to zero if rd_done_int is high
|
||||
//because there is no guarantee that nb_packets will be pos.
|
||||
|
||||
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
nb_packets <= 0;
|
||||
else if (wr_done_int & ~rd_done_int)
|
||||
nb_packets <= nb_packets + 3'd1;
|
||||
else if (rd_done_int & ~wr_done_int)
|
||||
nb_packets <= nb_packets - 3'd1;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,305 +0,0 @@
|
|||
module cmd_reader
|
||||
(//System
|
||||
input reset, input txclk, input [31:0] timestamp_clock,
|
||||
//FX2 Side
|
||||
output reg skip, output reg rdreq,
|
||||
input [31:0] fifodata, input pkt_waiting,
|
||||
//Rx side
|
||||
input rx_WR_enabled, output reg [15:0] rx_databus,
|
||||
output reg rx_WR, output reg rx_WR_done,
|
||||
//register io
|
||||
input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
|
||||
output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
|
||||
output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
|
||||
|
||||
// States
|
||||
parameter IDLE = 4'd0;
|
||||
parameter HEADER = 4'd1;
|
||||
parameter TIMESTAMP = 4'd2;
|
||||
parameter WAIT = 4'd3;
|
||||
parameter TEST = 4'd4;
|
||||
parameter SEND = 4'd5;
|
||||
parameter PING = 4'd6;
|
||||
parameter WRITE_REG = 4'd7;
|
||||
parameter WRITE_REG_MASKED = 4'd8;
|
||||
parameter READ_REG = 4'd9;
|
||||
parameter DELAY = 4'd14;
|
||||
|
||||
`define OP_PING_FIXED 8'd0
|
||||
`define OP_PING_FIXED_REPLY 8'd1
|
||||
`define OP_WRITE_REG 8'd2
|
||||
`define OP_WRITE_REG_MASKED 8'd3
|
||||
`define OP_READ_REG 8'd4
|
||||
`define OP_READ_REG_REPLY 8'd5
|
||||
`define OP_DELAY 8'd12
|
||||
|
||||
reg [6:0] payload;
|
||||
reg [6:0] payload_read;
|
||||
reg [3:0] state;
|
||||
reg [15:0] high;
|
||||
reg [15:0] low;
|
||||
reg pending;
|
||||
reg [31:0] value0;
|
||||
reg [31:0] value1;
|
||||
reg [31:0] value2;
|
||||
reg [1:0] lines_in;
|
||||
reg [1:0] lines_out;
|
||||
reg [1:0] lines_out_total;
|
||||
|
||||
`define JITTER 5
|
||||
`define OP_CODE 31:24
|
||||
`define PAYLOAD 8:2
|
||||
|
||||
wire [7:0] ops;
|
||||
assign ops = value0[`OP_CODE];
|
||||
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
begin
|
||||
pending <= 0;
|
||||
state <= IDLE;
|
||||
skip <= 0;
|
||||
rdreq <= 0;
|
||||
rx_WR <= 0;
|
||||
reg_io_enable <= 0;
|
||||
reg_data_in <= 0;
|
||||
reg_addr <= 0;
|
||||
stop <= 0;
|
||||
end
|
||||
else case (state)
|
||||
IDLE :
|
||||
begin
|
||||
payload_read <= 0;
|
||||
skip <= 0;
|
||||
lines_in <= 0;
|
||||
if(pkt_waiting)
|
||||
begin
|
||||
state <= HEADER;
|
||||
rdreq <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
HEADER :
|
||||
begin
|
||||
payload <= fifodata[`PAYLOAD];
|
||||
state <= TIMESTAMP;
|
||||
end
|
||||
|
||||
TIMESTAMP :
|
||||
begin
|
||||
value0 <= fifodata;
|
||||
state <= WAIT;
|
||||
rdreq <= 0;
|
||||
end
|
||||
|
||||
WAIT :
|
||||
begin
|
||||
// Let's send it
|
||||
if ((value0 <= timestamp_clock + `JITTER
|
||||
&& value0 > timestamp_clock)
|
||||
|| value0 == 32'hFFFFFFFF)
|
||||
state <= TEST;
|
||||
// Wait a little bit more
|
||||
else if (value0 > timestamp_clock + `JITTER)
|
||||
state <= WAIT;
|
||||
// Outdated
|
||||
else if (value0 < timestamp_clock)
|
||||
begin
|
||||
state <= IDLE;
|
||||
skip <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
TEST :
|
||||
begin
|
||||
reg_io_enable <= 0;
|
||||
rx_WR <= 0;
|
||||
rx_WR_done <= 1;
|
||||
stop <= 0;
|
||||
if (payload_read == payload)
|
||||
begin
|
||||
skip <= 1;
|
||||
state <= IDLE;
|
||||
rdreq <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
value0 <= fifodata;
|
||||
lines_in <= 2'd1;
|
||||
rdreq <= 1;
|
||||
payload_read <= payload_read + 7'd1;
|
||||
lines_out <= 0;
|
||||
case (fifodata[`OP_CODE])
|
||||
`OP_PING_FIXED:
|
||||
begin
|
||||
state <= PING;
|
||||
end
|
||||
`OP_WRITE_REG:
|
||||
begin
|
||||
state <= WRITE_REG;
|
||||
pending <= 1;
|
||||
end
|
||||
`OP_WRITE_REG_MASKED:
|
||||
begin
|
||||
state <= WRITE_REG_MASKED;
|
||||
pending <= 1;
|
||||
end
|
||||
`OP_READ_REG:
|
||||
begin
|
||||
state <= READ_REG;
|
||||
end
|
||||
`OP_DELAY:
|
||||
begin
|
||||
state <= DELAY;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
//error, skip this packet
|
||||
skip <= 1;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
SEND:
|
||||
begin
|
||||
rdreq <= 0;
|
||||
rx_WR_done <= 0;
|
||||
if (pending)
|
||||
begin
|
||||
rx_WR <= 1;
|
||||
rx_databus <= high;
|
||||
pending <= 0;
|
||||
if (lines_out == lines_out_total)
|
||||
state <= TEST;
|
||||
else case (ops)
|
||||
`OP_READ_REG:
|
||||
begin
|
||||
state <= READ_REG;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
state <= TEST;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (rx_WR_enabled)
|
||||
begin
|
||||
rx_WR <= 1;
|
||||
rx_databus <= low;
|
||||
pending <= 1;
|
||||
lines_out <= lines_out + 2'd1;
|
||||
end
|
||||
else
|
||||
rx_WR <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
PING:
|
||||
begin
|
||||
rx_WR <= 0;
|
||||
rdreq <= 0;
|
||||
rx_WR_done <= 0;
|
||||
lines_out_total <= 2'd1;
|
||||
pending <= 0;
|
||||
state <= SEND;
|
||||
high <= {`OP_PING_FIXED_REPLY, 8'd2};
|
||||
low <= value0[15:0];
|
||||
end
|
||||
|
||||
READ_REG:
|
||||
begin
|
||||
rx_WR <= 0;
|
||||
rx_WR_done <= 0;
|
||||
rdreq <= 0;
|
||||
lines_out_total <= 2'd2;
|
||||
pending <= 0;
|
||||
state <= SEND;
|
||||
if (lines_out == 0)
|
||||
begin
|
||||
high <= {`OP_READ_REG_REPLY, 8'd6};
|
||||
low <= value0[15:0];
|
||||
reg_io_enable <= 2'd3;
|
||||
reg_addr <= value0[6:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
high <= reg_data_out[31:16];
|
||||
low <= reg_data_out[15:0];
|
||||
end
|
||||
end
|
||||
|
||||
WRITE_REG:
|
||||
begin
|
||||
rx_WR <= 0;
|
||||
if (pending)
|
||||
pending <= 0;
|
||||
else
|
||||
begin
|
||||
if (lines_in == 2'd1)
|
||||
begin
|
||||
payload_read <= payload_read + 7'd1;
|
||||
lines_in <= lines_in + 2'd1;
|
||||
value1 <= fifodata;
|
||||
rdreq <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reg_io_enable <= 2'd2;
|
||||
reg_data_in <= value1;
|
||||
reg_addr <= value0[6:0];
|
||||
state <= TEST;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
WRITE_REG_MASKED:
|
||||
begin
|
||||
rx_WR <= 0;
|
||||
if (pending)
|
||||
pending <= 0;
|
||||
else
|
||||
begin
|
||||
if (lines_in == 2'd1)
|
||||
begin
|
||||
rdreq <= 1;
|
||||
payload_read <= payload_read + 7'd1;
|
||||
lines_in <= lines_in + 2'd1;
|
||||
value1 <= fifodata;
|
||||
end
|
||||
else if (lines_in == 2'd2)
|
||||
begin
|
||||
rdreq <= 0;
|
||||
payload_read <= payload_read + 7'd1;
|
||||
lines_in <= lines_in + 2'd1;
|
||||
value2 <= fifodata;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reg_io_enable <= 2'd2;
|
||||
reg_data_in <= (value1 & value2);
|
||||
reg_addr <= value0[6:0];
|
||||
state <= TEST;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
DELAY :
|
||||
begin
|
||||
rdreq <= 0;
|
||||
stop <= 1;
|
||||
stop_time <= value0[15:0];
|
||||
state <= TEST;
|
||||
end
|
||||
|
||||
default :
|
||||
begin
|
||||
//error state handling
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
|
@ -1,152 +0,0 @@
|
|||
module packet_builder #(parameter NUM_CHAN = 2)(
|
||||
// System
|
||||
input rxclk,
|
||||
input reset,
|
||||
input [31:0] timestamp_clock,
|
||||
input [3:0] channels,
|
||||
// ADC side
|
||||
input [15:0]chan_fifodata,
|
||||
input [NUM_CHAN:0]chan_empty,
|
||||
input [9:0]chan_usedw,
|
||||
output reg [3:0]rd_select,
|
||||
output reg chan_rdreq,
|
||||
// FX2 side
|
||||
output reg WR,
|
||||
output reg [15:0]fifodata,
|
||||
input have_space,
|
||||
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
|
||||
input wire [31:0]rssi_3, output wire [7:0] debugbus,
|
||||
input [NUM_CHAN:0] underrun);
|
||||
|
||||
|
||||
// States
|
||||
`define IDLE 3'd0
|
||||
`define HEADER1 3'd1
|
||||
`define HEADER2 3'd2
|
||||
`define TIMESTAMP 3'd3
|
||||
`define FORWARD 3'd4
|
||||
|
||||
`define MAXPAYLOAD 504
|
||||
|
||||
`define PAYLOAD_LEN 8:0
|
||||
`define TAG 12:9
|
||||
`define MBZ 15:13
|
||||
|
||||
`define CHAN 4:0
|
||||
`define RSSI 10:5
|
||||
`define BURST 12:11
|
||||
`define DROPPED 13
|
||||
`define UNDERRUN 14
|
||||
`define OVERRUN 15
|
||||
|
||||
reg [NUM_CHAN:0] overrun;
|
||||
reg [2:0] state;
|
||||
reg [8:0] read_length;
|
||||
reg [8:0] payload_len;
|
||||
reg timestamp_complete;
|
||||
reg [3:0] check_next;
|
||||
|
||||
wire [31:0] true_rssi;
|
||||
wire [4:0] true_channel;
|
||||
wire ready_to_send;
|
||||
|
||||
assign debugbus = {chan_empty[0], rd_select[0], have_space,
|
||||
(chan_usedw >= 10'd504), (chan_usedw ==0),
|
||||
ready_to_send, state[1:0]};
|
||||
|
||||
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
|
||||
((rd_select[0]) ? rssi_1:rssi_0);
|
||||
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
|
||||
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
|
||||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
|
||||
|
||||
always @(posedge rxclk)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
overrun <= 0;
|
||||
WR <= 0;
|
||||
rd_select <= 0;
|
||||
chan_rdreq <= 0;
|
||||
timestamp_complete <= 0;
|
||||
check_next <= 0;
|
||||
state <= `IDLE;
|
||||
end
|
||||
else case (state)
|
||||
`IDLE: begin
|
||||
chan_rdreq <= #1 0;
|
||||
//check if the channel is full
|
||||
if(~chan_empty[check_next])
|
||||
begin
|
||||
if (have_space)
|
||||
begin
|
||||
//transmit if the usb buffer have space
|
||||
//check if we should send
|
||||
if (ready_to_send)
|
||||
state <= #1 `HEADER1;
|
||||
|
||||
overrun[check_next] <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state <= #1 `IDLE;
|
||||
overrun[check_next] <= 1;
|
||||
end
|
||||
rd_select <= #1 check_next;
|
||||
end
|
||||
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
|
||||
end
|
||||
|
||||
`HEADER1: begin
|
||||
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
|
||||
payload_len <= #1 9'd504;
|
||||
fifodata[`TAG] <= #1 0;
|
||||
fifodata[`MBZ] <= #1 0;
|
||||
WR <= #1 1;
|
||||
|
||||
state <= #1 `HEADER2;
|
||||
read_length <= #1 0;
|
||||
end
|
||||
|
||||
`HEADER2: begin
|
||||
fifodata[`CHAN] <= #1 true_channel;
|
||||
fifodata[`RSSI] <= #1 true_rssi[5:0];
|
||||
fifodata[`BURST] <= #1 0;
|
||||
fifodata[`DROPPED] <= #1 0;
|
||||
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
|
||||
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
|
||||
state <= #1 `TIMESTAMP;
|
||||
end
|
||||
|
||||
`TIMESTAMP: begin
|
||||
fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
|
||||
timestamp_complete <= #1 ~timestamp_complete;
|
||||
|
||||
if (~timestamp_complete)
|
||||
chan_rdreq <= #1 1;
|
||||
|
||||
state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
|
||||
end
|
||||
|
||||
`FORWARD: begin
|
||||
read_length <= #1 read_length + 9'd2;
|
||||
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
|
||||
|
||||
if (read_length >= `MAXPAYLOAD)
|
||||
begin
|
||||
WR <= #1 0;
|
||||
state <= #1 `IDLE;
|
||||
chan_rdreq <= #1 0;
|
||||
end
|
||||
else if (read_length == payload_len - 4)
|
||||
chan_rdreq <= #1 0;
|
||||
end
|
||||
|
||||
default: begin
|
||||
//handling error state
|
||||
state <= `IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
module register_io
|
||||
(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
|
||||
rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
|
||||
debug_en, misc, txmux);
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
input wire [1:0] enable;
|
||||
input wire [6:0] addr;
|
||||
input wire [31:0] datain;
|
||||
output reg [31:0] dataout;
|
||||
output wire [15:0] debugbus;
|
||||
output reg [6:0] addr_wr;
|
||||
output reg [31:0] data_wr;
|
||||
output wire strobe_wr;
|
||||
input wire [31:0] rssi_0;
|
||||
input wire [31:0] rssi_1;
|
||||
input wire [31:0] rssi_2;
|
||||
input wire [31:0] rssi_3;
|
||||
output wire [31:0] threshhold;
|
||||
output wire [31:0] rssi_wait;
|
||||
input wire [15:0] reg_0;
|
||||
input wire [15:0] reg_1;
|
||||
input wire [15:0] reg_2;
|
||||
input wire [15:0] reg_3;
|
||||
input wire [3:0] debug_en;
|
||||
input wire [7:0] misc;
|
||||
input wire [31:0] txmux;
|
||||
|
||||
reg strobe;
|
||||
wire [31:0] out[2:1];
|
||||
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
|
||||
assign threshhold = out[1];
|
||||
assign rssi_wait = out[2];
|
||||
assign strobe_wr = strobe;
|
||||
|
||||
always @(*)
|
||||
if (reset | ~enable[1])
|
||||
begin
|
||||
strobe <= 0;
|
||||
dataout <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (enable[0])
|
||||
begin
|
||||
//read
|
||||
if (addr <= 7'd52 && addr > 7'd50)
|
||||
dataout <= out[addr-7'd50];
|
||||
else
|
||||
dataout <= 32'hFFFFFFFF;
|
||||
strobe <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//write
|
||||
dataout <= dataout;
|
||||
strobe <= 1;
|
||||
data_wr <= datain;
|
||||
addr_wr <= addr;
|
||||
end
|
||||
end
|
||||
|
||||
//register declarations
|
||||
/*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
|
||||
setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
|
||||
setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
|
||||
/*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
|
||||
setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
|
||||
setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
|
||||
setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
|
||||
setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
|
||||
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
//`include "../../firmware/include/fpga_regs_common.v"
|
||||
//`include "../../firmware/include/fpga_regs_standard.v"
|
||||
module rx_buffer_inband
|
||||
( input usbclk,
|
||||
input bus_reset,
|
||||
input reset, // DSP side reset (used here), do not reset registers
|
||||
input reset_regs, //Only reset registers
|
||||
output [15:0] usbdata,
|
||||
input RD,
|
||||
output wire have_pkt_rdy,
|
||||
output reg rx_overrun,
|
||||
input wire [3:0] channels,
|
||||
input wire [15:0] ch_0,
|
||||
input wire [15:0] ch_1,
|
||||
input wire [15:0] ch_2,
|
||||
input wire [15:0] ch_3,
|
||||
input wire [15:0] ch_4,
|
||||
input wire [15:0] ch_5,
|
||||
input wire [15:0] ch_6,
|
||||
input wire [15:0] ch_7,
|
||||
input rxclk,
|
||||
input rxstrobe,
|
||||
input clear_status,
|
||||
input [6:0] serial_addr,
|
||||
input [31:0] serial_data,
|
||||
input serial_strobe,
|
||||
output wire [15:0] debugbus,
|
||||
|
||||
//Connection with tx_inband
|
||||
input rx_WR,
|
||||
input [15:0] rx_databus,
|
||||
input rx_WR_done,
|
||||
output reg rx_WR_enabled,
|
||||
//signal strength
|
||||
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
|
||||
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
|
||||
input wire [1:0] tx_underrun
|
||||
);
|
||||
|
||||
parameter NUM_CHAN = 1;
|
||||
genvar i ;
|
||||
|
||||
// FX2 Bug Fix
|
||||
reg [8:0] read_count;
|
||||
always @(negedge usbclk)
|
||||
if(bus_reset)
|
||||
read_count <= #1 9'd0;
|
||||
else if(RD & ~read_count[8])
|
||||
read_count <= #1 read_count + 9'd1;
|
||||
else
|
||||
read_count <= #1 RD ? read_count : 9'b0;
|
||||
|
||||
// Time counter
|
||||
reg [31:0] timestamp_clock;
|
||||
always @(posedge rxclk)
|
||||
if (reset)
|
||||
timestamp_clock <= 0;
|
||||
else
|
||||
timestamp_clock <= timestamp_clock + 1;
|
||||
|
||||
// USB side fifo
|
||||
wire [11:0] rdusedw;
|
||||
wire [11:0] wrusedw;
|
||||
wire [15:0] fifodata;
|
||||
wire [15:0] fifodata_il[0:NUM_CHAN];
|
||||
wire WR;
|
||||
wire have_space;
|
||||
reg sel;
|
||||
reg wr;
|
||||
|
||||
always@(posedge rxclk)
|
||||
begin
|
||||
if(reset)
|
||||
begin
|
||||
sel<=1;
|
||||
wr<=0;
|
||||
end
|
||||
else if(rxstrobe)
|
||||
begin
|
||||
sel<=0;
|
||||
wr<=1;
|
||||
end
|
||||
else if(wr&~sel)
|
||||
sel<=1;
|
||||
else if(wr&sel)
|
||||
wr<=0;
|
||||
else
|
||||
wr<=0;
|
||||
end
|
||||
|
||||
assign fifodata_il[0] = (sel)?ch_1:ch_0;
|
||||
assign fifodata_il[1] = (sel)?ch_3:ch_2;
|
||||
|
||||
fifo_4kx16_dc rx_usb_fifo (
|
||||
.aclr ( reset ),
|
||||
.data ( fifodata ),
|
||||
.rdclk ( ~usbclk ),
|
||||
.rdreq ( RD & ~read_count[8] ),
|
||||
.wrclk ( rxclk ),
|
||||
.wrreq ( WR ),
|
||||
.q ( usbdata ),
|
||||
.rdempty ( ),
|
||||
.rdusedw ( rdusedw ),
|
||||
.wrfull ( ),
|
||||
.wrusedw ( wrusedw ) );
|
||||
|
||||
assign have_pkt_rdy = (rdusedw >= 12'd256);
|
||||
assign have_space = (wrusedw < 12'd760);
|
||||
|
||||
// Rx side fifos
|
||||
// These are of size [NUM_CHAN:0] because the extra channel is used for the
|
||||
// RX command channel. If there were no command channel, they would be
|
||||
// NUM_CHAN-1.
|
||||
wire chan_rdreq;
|
||||
wire [15:0] chan_fifodata;
|
||||
wire [9:0] chan_usedw;
|
||||
wire [NUM_CHAN:0] chan_empty;
|
||||
wire [3:0] rd_select;
|
||||
wire [NUM_CHAN:0] rx_full;
|
||||
|
||||
packet_builder #(NUM_CHAN) rx_pkt_builer (
|
||||
.rxclk ( rxclk ),
|
||||
.reset ( reset ),
|
||||
.timestamp_clock ( timestamp_clock ),
|
||||
.channels ( NUM_CHAN ),
|
||||
.chan_rdreq ( chan_rdreq ),
|
||||
.chan_fifodata ( chan_fifodata ),
|
||||
.chan_empty ( chan_empty ),
|
||||
.rd_select ( rd_select ),
|
||||
.chan_usedw ( chan_usedw ),
|
||||
.WR ( WR ),
|
||||
.fifodata ( fifodata ),
|
||||
.have_space ( have_space ),
|
||||
.rssi_0(rssi_0), .rssi_1(rssi_1),
|
||||
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
|
||||
.underrun(tx_underrun));
|
||||
|
||||
// Detect overrun
|
||||
always @(posedge rxclk)
|
||||
if(reset)
|
||||
rx_overrun <= 1'b0;
|
||||
else if(rx_full[0])
|
||||
rx_overrun <= 1'b1;
|
||||
else if(clear_status)
|
||||
rx_overrun <= 1'b0;
|
||||
|
||||
|
||||
// FIXME: what is the purpose of these two lines?
|
||||
wire [15:0]ch[NUM_CHAN:0];
|
||||
assign ch[0] = ch_0;
|
||||
|
||||
wire cmd_empty;
|
||||
|
||||
always @(posedge rxclk)
|
||||
if(reset)
|
||||
rx_WR_enabled <= 1;
|
||||
else if(cmd_empty)
|
||||
rx_WR_enabled <= 1;
|
||||
else if(rx_WR_done)
|
||||
rx_WR_enabled <= 0;
|
||||
|
||||
|
||||
// Of Size 0:NUM_CHAN due to extra command channel.
|
||||
wire [15:0] dataout [0:NUM_CHAN];
|
||||
wire [9:0] usedw [0:NUM_CHAN];
|
||||
wire empty[0:NUM_CHAN];
|
||||
|
||||
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
|
||||
begin : generate_channel_fifos
|
||||
|
||||
wire rdreq;
|
||||
|
||||
assign rdreq = (rd_select == i) & chan_rdreq;
|
||||
|
||||
fifo_1kx16 rx_chan_fifo (
|
||||
.aclr ( reset ),
|
||||
.clock ( rxclk ),
|
||||
.data ( fifodata_il[i] ),
|
||||
.rdreq ( rdreq ),
|
||||
.wrreq ( ~rx_full[i] & wr),
|
||||
.empty (empty[i]),
|
||||
.full (rx_full[i]),
|
||||
.q ( dataout[i]),
|
||||
.usedw ( usedw[i]),
|
||||
.almost_empty(chan_empty[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire [7:0] debug;
|
||||
|
||||
fifo_1kx16 rx_cmd_fifo (
|
||||
.aclr ( reset ),
|
||||
.clock ( rxclk ),
|
||||
.data ( rx_databus ),
|
||||
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
|
||||
.wrreq ( rx_WR & rx_WR_enabled),
|
||||
.empty ( cmd_empty),
|
||||
.full ( rx_full[NUM_CHAN] ),
|
||||
.q ( dataout[NUM_CHAN]),
|
||||
.usedw ( usedw[NUM_CHAN] )
|
||||
);
|
||||
|
||||
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
|
||||
assign chan_fifodata = dataout[rd_select];
|
||||
assign chan_usedw = usedw[rd_select];
|
||||
assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
module tx_buffer_inband
|
||||
( //System
|
||||
input wire usbclk, input wire bus_reset, input wire reset,
|
||||
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
|
||||
//output transmit signals
|
||||
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
|
||||
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
|
||||
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
|
||||
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
|
||||
input wire txclk, input wire txstrobe, input wire WR,
|
||||
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
|
||||
//command reader io
|
||||
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
|
||||
input wire rx_WR_enabled,
|
||||
//register io
|
||||
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
|
||||
input wire [31:0] reg_data_out,
|
||||
//input characteristic signals
|
||||
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
|
||||
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
|
||||
output wire [1:0] tx_underrun,
|
||||
//system stop
|
||||
output wire stop, output wire [15:0] stop_time);
|
||||
|
||||
parameter NUM_CHAN = 1 ;
|
||||
|
||||
/* To generate channel readers */
|
||||
genvar i ;
|
||||
|
||||
/* These will eventually be external register */
|
||||
reg [31:0] timestamp_clock ;
|
||||
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
|
||||
wire [31:0] rssi [3:0];
|
||||
assign rssi[0] = rssi_0;
|
||||
assign rssi[1] = rssi_1;
|
||||
assign rssi[2] = rssi_2;
|
||||
assign rssi[3] = rssi_3;
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
timestamp_clock <= 0;
|
||||
else
|
||||
timestamp_clock <= timestamp_clock + 1;
|
||||
|
||||
|
||||
/* Connections between tx_usb_fifo_reader and
|
||||
cnannel/command processing blocks */
|
||||
wire [31:0] tx_data_bus ;
|
||||
wire [NUM_CHAN:0] chan_WR ;
|
||||
wire [NUM_CHAN:0] chan_done ;
|
||||
|
||||
/* Connections between data block and the
|
||||
FX2/TX chains */
|
||||
wire [NUM_CHAN:0] chan_underrun;
|
||||
wire [NUM_CHAN:0] chan_txempty;
|
||||
|
||||
/* Conections between tx_data_packet_fifo and
|
||||
its reader + strobe generator */
|
||||
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
|
||||
wire chan_pkt_waiting [NUM_CHAN:0] ;
|
||||
wire chan_rdreq [NUM_CHAN:0] ;
|
||||
wire chan_skip [NUM_CHAN:0] ;
|
||||
wire chan_have_space [NUM_CHAN:0] ;
|
||||
|
||||
wire [14:0] debug [NUM_CHAN:0];
|
||||
|
||||
/* Outputs to transmit chains */
|
||||
wire [15:0] tx_i [NUM_CHAN:0] ;
|
||||
wire [15:0] tx_q [NUM_CHAN:0] ;
|
||||
|
||||
assign tx_i[NUM_CHAN] = 0;
|
||||
assign tx_q[NUM_CHAN] = 0;
|
||||
|
||||
assign have_space = chan_have_space[0] & chan_have_space[1];
|
||||
assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
|
||||
|
||||
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
|
||||
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
|
||||
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
|
||||
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
|
||||
|
||||
assign tx_q_2 = 16'b0 ;
|
||||
assign tx_i_2 = 16'b0 ;
|
||||
assign tx_q_3 = 16'b0 ;
|
||||
assign tx_i_3 = 16'b0 ;
|
||||
assign tx_i_3 = 16'b0 ;
|
||||
|
||||
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
|
||||
chan_pkt_waiting[0], chan_pkt_waiting[1],
|
||||
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
|
||||
|
||||
wire [31:0] usbdata_final;
|
||||
wire WR_final;
|
||||
|
||||
tx_packer tx_usb_packer
|
||||
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
|
||||
.usbdata(usbdata), .reset(reset), .txclk(txclk),
|
||||
.usbdata_final(usbdata_final), .WR_final(WR_final));
|
||||
|
||||
channel_demux #(NUM_CHAN) channel_demuxer
|
||||
(.usbdata_final(usbdata_final), .WR_final(WR_final),
|
||||
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
|
||||
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
|
||||
|
||||
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
|
||||
begin : generate_channel_readers
|
||||
assign tx_underrun[i] = chan_underrun[i];
|
||||
|
||||
channel_ram tx_data_packet_fifo
|
||||
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
|
||||
.WR(chan_WR[i]), .WR_done(chan_done[i]),
|
||||
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
|
||||
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
|
||||
.RD_done(chan_skip[i]));
|
||||
|
||||
chan_fifo_reader tx_chan_reader
|
||||
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
|
||||
.timestamp_clock(timestamp_clock), .samples_format(4'b0),
|
||||
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
|
||||
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
|
||||
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
|
||||
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
|
||||
.threshhold(threshhold), .rssi_wait(rssi_wait));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
channel_ram tx_cmd_packet_fifo
|
||||
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
|
||||
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
|
||||
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
|
||||
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
|
||||
|
||||
cmd_reader tx_cmd_reader
|
||||
(.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]),
|
||||
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
|
||||
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
|
||||
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
|
||||
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
|
||||
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
|
||||
|
||||
endmodule // tx_buffer
|
||||
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
module tx_packer
|
||||
( //FX2 Side
|
||||
input bus_reset,
|
||||
input usbclk,
|
||||
input WR_fx2,
|
||||
input [15:0]usbdata,
|
||||
|
||||
// TX Side
|
||||
input reset,
|
||||
input txclk,
|
||||
output reg [31:0] usbdata_final,
|
||||
output reg WR_final);
|
||||
|
||||
reg [8:0] write_count;
|
||||
|
||||
/* Fix FX2 bug */
|
||||
always @(posedge usbclk)
|
||||
begin
|
||||
if(bus_reset) // Use bus reset because this is on usbclk
|
||||
write_count <= #1 0;
|
||||
else if(WR_fx2 & ~write_count[8])
|
||||
write_count <= #1 write_count + 9'd1;
|
||||
else
|
||||
write_count <= #1 WR_fx2 ? write_count : 9'b0;
|
||||
end
|
||||
|
||||
reg WR_fx2_fixed;
|
||||
reg [15:0]usbdata_fixed;
|
||||
|
||||
always @(posedge usbclk)
|
||||
begin
|
||||
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
|
||||
usbdata_fixed <= usbdata;
|
||||
end
|
||||
|
||||
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
|
||||
reg word_complete ;
|
||||
reg [15:0] usbdata_delayed ;
|
||||
reg writing ;
|
||||
wire [31:0] usbdata_packed ;
|
||||
wire WR_packed ;
|
||||
|
||||
always @(posedge usbclk)
|
||||
begin
|
||||
if (bus_reset)
|
||||
begin
|
||||
word_complete <= 0 ;
|
||||
writing <= 0 ;
|
||||
end
|
||||
else if (WR_fx2_fixed)
|
||||
begin
|
||||
writing <= 1 ;
|
||||
if (word_complete)
|
||||
word_complete <= 0 ;
|
||||
else
|
||||
begin
|
||||
usbdata_delayed <= usbdata_fixed ;
|
||||
word_complete <= 1 ;
|
||||
end
|
||||
end
|
||||
else
|
||||
writing <= 0 ;
|
||||
end
|
||||
|
||||
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
|
||||
assign WR_packed = word_complete & writing ;
|
||||
|
||||
/* Make sure data are sync with usbclk */
|
||||
reg [31:0]usbdata_usbclk;
|
||||
reg WR_usbclk;
|
||||
|
||||
always @(posedge usbclk)
|
||||
begin
|
||||
if (WR_packed)
|
||||
usbdata_usbclk <= usbdata_packed;
|
||||
WR_usbclk <= WR_packed;
|
||||
end
|
||||
|
||||
/* Cross clock boundaries */
|
||||
reg [31:0] usbdata_tx ;
|
||||
reg WR_tx;
|
||||
reg WR_1;
|
||||
reg WR_2;
|
||||
|
||||
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
WR_1 <= 0;
|
||||
else
|
||||
WR_1 <= WR_usbclk;
|
||||
|
||||
always @(posedge txclk)
|
||||
if (reset)
|
||||
WR_2 <= 0;
|
||||
else
|
||||
WR_2 <= WR_1;
|
||||
|
||||
always @(posedge txclk)
|
||||
begin
|
||||
if (reset)
|
||||
WR_tx <= 0;
|
||||
else
|
||||
WR_tx <= WR_1 & ~WR_2;
|
||||
end
|
||||
|
||||
always @(posedge txclk)
|
||||
begin
|
||||
if (reset)
|
||||
WR_final <= 0;
|
||||
else
|
||||
begin
|
||||
WR_final <= WR_tx;
|
||||
if (WR_tx)
|
||||
usbdata_final <= usbdata_tx;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
module usb_packet_fifo
|
||||
( input reset,
|
||||
input clock_in,
|
||||
input clock_out,
|
||||
input [15:0]ram_data_in,
|
||||
input write_enable,
|
||||
output reg [15:0]ram_data_out,
|
||||
output reg pkt_waiting,
|
||||
output reg have_space,
|
||||
input read_enable,
|
||||
input skip_packet ) ;
|
||||
|
||||
/* Some parameters for usage later on */
|
||||
parameter DATA_WIDTH = 16 ;
|
||||
parameter NUM_PACKETS = 4 ;
|
||||
|
||||
/* Create the RAM here */
|
||||
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
|
||||
|
||||
/* Create the address signals */
|
||||
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
|
||||
reg [7:0] usb_ram_offset ;
|
||||
reg [1:0] usb_ram_packet ;
|
||||
|
||||
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
|
||||
reg isfull;
|
||||
|
||||
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
|
||||
|
||||
// Check if there is one full packet to process
|
||||
always @(usb_ram_ain, usb_ram_aout)
|
||||
begin
|
||||
if (reset)
|
||||
pkt_waiting <= 0;
|
||||
else if (usb_ram_ain == usb_ram_aout)
|
||||
pkt_waiting <= isfull;
|
||||
else if (usb_ram_ain > usb_ram_aout)
|
||||
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
|
||||
else
|
||||
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
|
||||
end
|
||||
|
||||
// Check if there is room
|
||||
always @(usb_ram_ain, usb_ram_aout)
|
||||
begin
|
||||
if (reset)
|
||||
have_space <= 1;
|
||||
else if (usb_ram_ain == usb_ram_aout)
|
||||
have_space <= ~isfull;
|
||||
else if (usb_ram_ain > usb_ram_aout)
|
||||
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
|
||||
else
|
||||
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
|
||||
end
|
||||
|
||||
/* RAM Write Address process */
|
||||
always @(posedge clock_in)
|
||||
begin
|
||||
if( reset )
|
||||
usb_ram_ain <= 0 ;
|
||||
else
|
||||
if( write_enable )
|
||||
begin
|
||||
usb_ram_ain <= usb_ram_ain + 1 ;
|
||||
if (usb_ram_ain + 1 == usb_ram_aout)
|
||||
isfull <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
/* RAM Writing process */
|
||||
always @(posedge clock_in)
|
||||
begin
|
||||
if( write_enable )
|
||||
begin
|
||||
usb_ram[usb_ram_ain] <= ram_data_in ;
|
||||
end
|
||||
end
|
||||
|
||||
/* RAM Read Address process */
|
||||
always @(posedge clock_out)
|
||||
begin
|
||||
if( reset )
|
||||
begin
|
||||
usb_ram_packet <= 0 ;
|
||||
usb_ram_offset <= 0 ;
|
||||
isfull <= 0;
|
||||
end
|
||||
else
|
||||
if( skip_packet )
|
||||
begin
|
||||
usb_ram_packet <= usb_ram_packet + 1 ;
|
||||
usb_ram_offset <= 0 ;
|
||||
end
|
||||
else if(read_enable)
|
||||
if( usb_ram_offset == 8'b11111111 )
|
||||
begin
|
||||
usb_ram_offset <= 0 ;
|
||||
usb_ram_packet <= usb_ram_packet + 1 ;
|
||||
end
|
||||
else
|
||||
usb_ram_offset <= usb_ram_offset + 1 ;
|
||||
if (usb_ram_ain == usb_ram_aout)
|
||||
isfull <= 0;
|
||||
end
|
||||
|
||||
/* RAM Reading Process */
|
||||
always @(posedge clock_out)
|
||||
begin
|
||||
ram_data_out <= usb_ram[usb_ram_aout] ;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1 +0,0 @@
|
|||
/db
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 240 120)
|
||||
(text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 101 31 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
|
||||
(text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 16 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 240 56)
|
||||
(output)
|
||||
(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 240 56)(pt 224 56)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8)))
|
||||
(text "SIGNED" (rect 177 18 214 32)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 224 16)(line_width 1))
|
||||
(line (pt 16 16)(pt 16 104)(line_width 1))
|
||||
(line (pt 16 104)(pt 224 104)(line_width 1))
|
||||
(line (pt 224 16)(pt 224 104)(line_width 1))
|
||||
(line (pt 88 24)(pt 136 48)(line_width 1))
|
||||
(line (pt 136 64)(pt 136 48)(line_width 1))
|
||||
(line (pt 88 88)(pt 136 64)(line_width 1))
|
||||
(line (pt 88 24)(pt 88 88)(line_width 1))
|
||||
(line (pt 16 40)(pt 88 40)(line_width 1))
|
||||
(line (pt 16 56)(pt 88 56)(line_width 1))
|
||||
(line (pt 136 56)(pt 224 56)(line_width 1))
|
||||
(line (pt 16 72)(pt 88 72)(line_width 1))
|
||||
(line (pt 16 72)(pt 88 72)(line_width 1))
|
||||
(line (pt 16 96)(pt 104 96)(line_width 1))
|
||||
(line (pt 104 96)(pt 104 80)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component accum32
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
clock : IN STD_LOGIC := '0';
|
||||
clken : IN STD_LOGIC := '1';
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION accum32
|
||||
(
|
||||
data[31..0],
|
||||
clock,
|
||||
clken,
|
||||
aclr
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[31..0]
|
||||
);
|
||||
|
|
@ -1,765 +0,0 @@
|
|||
// megafunction wizard: %ALTACCUMULATE%CBX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altaccumulate
|
||||
|
||||
// ============================================================
|
||||
// File Name: accum32.v
|
||||
// Megafunction Name(s):
|
||||
// altaccumulate
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
|
||||
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
|
||||
|
||||
//synthesis_resources = lut 32
|
||||
module accum32_accum_nta
|
||||
(
|
||||
aclr,
|
||||
clken,
|
||||
clock,
|
||||
data,
|
||||
result) /* synthesis synthesis_clearbox=1 */;
|
||||
input aclr;
|
||||
input clken;
|
||||
input clock;
|
||||
input [31:0] data;
|
||||
output [31:0] result;
|
||||
|
||||
wire [0:0] wire_acc_cella_0cout;
|
||||
wire [0:0] wire_acc_cella_1cout;
|
||||
wire [0:0] wire_acc_cella_2cout;
|
||||
wire [0:0] wire_acc_cella_3cout;
|
||||
wire [0:0] wire_acc_cella_4cout;
|
||||
wire [0:0] wire_acc_cella_5cout;
|
||||
wire [0:0] wire_acc_cella_6cout;
|
||||
wire [0:0] wire_acc_cella_7cout;
|
||||
wire [0:0] wire_acc_cella_8cout;
|
||||
wire [0:0] wire_acc_cella_9cout;
|
||||
wire [0:0] wire_acc_cella_10cout;
|
||||
wire [0:0] wire_acc_cella_11cout;
|
||||
wire [0:0] wire_acc_cella_12cout;
|
||||
wire [0:0] wire_acc_cella_13cout;
|
||||
wire [0:0] wire_acc_cella_14cout;
|
||||
wire [0:0] wire_acc_cella_15cout;
|
||||
wire [0:0] wire_acc_cella_16cout;
|
||||
wire [0:0] wire_acc_cella_17cout;
|
||||
wire [0:0] wire_acc_cella_18cout;
|
||||
wire [0:0] wire_acc_cella_19cout;
|
||||
wire [0:0] wire_acc_cella_20cout;
|
||||
wire [0:0] wire_acc_cella_21cout;
|
||||
wire [0:0] wire_acc_cella_22cout;
|
||||
wire [0:0] wire_acc_cella_23cout;
|
||||
wire [0:0] wire_acc_cella_24cout;
|
||||
wire [0:0] wire_acc_cella_25cout;
|
||||
wire [0:0] wire_acc_cella_26cout;
|
||||
wire [0:0] wire_acc_cella_27cout;
|
||||
wire [0:0] wire_acc_cella_28cout;
|
||||
wire [0:0] wire_acc_cella_29cout;
|
||||
wire [0:0] wire_acc_cella_30cout;
|
||||
wire [31:0] wire_acc_cella_dataa;
|
||||
wire [31:0] wire_acc_cella_datab;
|
||||
wire [31:0] wire_acc_cella_datac;
|
||||
wire [31:0] wire_acc_cella_regout;
|
||||
wire sload;
|
||||
|
||||
stratix_lcell acc_cella_0
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(1'b0),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_0cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[0:0]),
|
||||
.datab(wire_acc_cella_datab[0:0]),
|
||||
.datac(wire_acc_cella_datac[0:0]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[0:0]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_0.cin_used = "true",
|
||||
acc_cella_0.lut_mask = "96e8",
|
||||
acc_cella_0.operation_mode = "arithmetic",
|
||||
acc_cella_0.sum_lutc_input = "cin",
|
||||
acc_cella_0.synch_mode = "on",
|
||||
acc_cella_0.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_1
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_0cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_1cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[1:1]),
|
||||
.datab(wire_acc_cella_datab[1:1]),
|
||||
.datac(wire_acc_cella_datac[1:1]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[1:1]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_1.cin_used = "true",
|
||||
acc_cella_1.lut_mask = "96e8",
|
||||
acc_cella_1.operation_mode = "arithmetic",
|
||||
acc_cella_1.sum_lutc_input = "cin",
|
||||
acc_cella_1.synch_mode = "on",
|
||||
acc_cella_1.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_2
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_1cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_2cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[2:2]),
|
||||
.datab(wire_acc_cella_datab[2:2]),
|
||||
.datac(wire_acc_cella_datac[2:2]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[2:2]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_2.cin_used = "true",
|
||||
acc_cella_2.lut_mask = "96e8",
|
||||
acc_cella_2.operation_mode = "arithmetic",
|
||||
acc_cella_2.sum_lutc_input = "cin",
|
||||
acc_cella_2.synch_mode = "on",
|
||||
acc_cella_2.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_3
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_2cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_3cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[3:3]),
|
||||
.datab(wire_acc_cella_datab[3:3]),
|
||||
.datac(wire_acc_cella_datac[3:3]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[3:3]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_3.cin_used = "true",
|
||||
acc_cella_3.lut_mask = "96e8",
|
||||
acc_cella_3.operation_mode = "arithmetic",
|
||||
acc_cella_3.sum_lutc_input = "cin",
|
||||
acc_cella_3.synch_mode = "on",
|
||||
acc_cella_3.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_4
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_3cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_4cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[4:4]),
|
||||
.datab(wire_acc_cella_datab[4:4]),
|
||||
.datac(wire_acc_cella_datac[4:4]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[4:4]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_4.cin_used = "true",
|
||||
acc_cella_4.lut_mask = "96e8",
|
||||
acc_cella_4.operation_mode = "arithmetic",
|
||||
acc_cella_4.sum_lutc_input = "cin",
|
||||
acc_cella_4.synch_mode = "on",
|
||||
acc_cella_4.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_5
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_4cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_5cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[5:5]),
|
||||
.datab(wire_acc_cella_datab[5:5]),
|
||||
.datac(wire_acc_cella_datac[5:5]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[5:5]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_5.cin_used = "true",
|
||||
acc_cella_5.lut_mask = "96e8",
|
||||
acc_cella_5.operation_mode = "arithmetic",
|
||||
acc_cella_5.sum_lutc_input = "cin",
|
||||
acc_cella_5.synch_mode = "on",
|
||||
acc_cella_5.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_6
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_5cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_6cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[6:6]),
|
||||
.datab(wire_acc_cella_datab[6:6]),
|
||||
.datac(wire_acc_cella_datac[6:6]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[6:6]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_6.cin_used = "true",
|
||||
acc_cella_6.lut_mask = "96e8",
|
||||
acc_cella_6.operation_mode = "arithmetic",
|
||||
acc_cella_6.sum_lutc_input = "cin",
|
||||
acc_cella_6.synch_mode = "on",
|
||||
acc_cella_6.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_7
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_6cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_7cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[7:7]),
|
||||
.datab(wire_acc_cella_datab[7:7]),
|
||||
.datac(wire_acc_cella_datac[7:7]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[7:7]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_7.cin_used = "true",
|
||||
acc_cella_7.lut_mask = "96e8",
|
||||
acc_cella_7.operation_mode = "arithmetic",
|
||||
acc_cella_7.sum_lutc_input = "cin",
|
||||
acc_cella_7.synch_mode = "on",
|
||||
acc_cella_7.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_8
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_7cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_8cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[8:8]),
|
||||
.datab(wire_acc_cella_datab[8:8]),
|
||||
.datac(wire_acc_cella_datac[8:8]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[8:8]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_8.cin_used = "true",
|
||||
acc_cella_8.lut_mask = "96e8",
|
||||
acc_cella_8.operation_mode = "arithmetic",
|
||||
acc_cella_8.sum_lutc_input = "cin",
|
||||
acc_cella_8.synch_mode = "on",
|
||||
acc_cella_8.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_9
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_8cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_9cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[9:9]),
|
||||
.datab(wire_acc_cella_datab[9:9]),
|
||||
.datac(wire_acc_cella_datac[9:9]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[9:9]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_9.cin_used = "true",
|
||||
acc_cella_9.lut_mask = "96e8",
|
||||
acc_cella_9.operation_mode = "arithmetic",
|
||||
acc_cella_9.sum_lutc_input = "cin",
|
||||
acc_cella_9.synch_mode = "on",
|
||||
acc_cella_9.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_10
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_9cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_10cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[10:10]),
|
||||
.datab(wire_acc_cella_datab[10:10]),
|
||||
.datac(wire_acc_cella_datac[10:10]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[10:10]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_10.cin_used = "true",
|
||||
acc_cella_10.lut_mask = "96e8",
|
||||
acc_cella_10.operation_mode = "arithmetic",
|
||||
acc_cella_10.sum_lutc_input = "cin",
|
||||
acc_cella_10.synch_mode = "on",
|
||||
acc_cella_10.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_11
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_10cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_11cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[11:11]),
|
||||
.datab(wire_acc_cella_datab[11:11]),
|
||||
.datac(wire_acc_cella_datac[11:11]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[11:11]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_11.cin_used = "true",
|
||||
acc_cella_11.lut_mask = "96e8",
|
||||
acc_cella_11.operation_mode = "arithmetic",
|
||||
acc_cella_11.sum_lutc_input = "cin",
|
||||
acc_cella_11.synch_mode = "on",
|
||||
acc_cella_11.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_12
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_11cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_12cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[12:12]),
|
||||
.datab(wire_acc_cella_datab[12:12]),
|
||||
.datac(wire_acc_cella_datac[12:12]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[12:12]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_12.cin_used = "true",
|
||||
acc_cella_12.lut_mask = "96e8",
|
||||
acc_cella_12.operation_mode = "arithmetic",
|
||||
acc_cella_12.sum_lutc_input = "cin",
|
||||
acc_cella_12.synch_mode = "on",
|
||||
acc_cella_12.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_13
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_12cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_13cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[13:13]),
|
||||
.datab(wire_acc_cella_datab[13:13]),
|
||||
.datac(wire_acc_cella_datac[13:13]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[13:13]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_13.cin_used = "true",
|
||||
acc_cella_13.lut_mask = "96e8",
|
||||
acc_cella_13.operation_mode = "arithmetic",
|
||||
acc_cella_13.sum_lutc_input = "cin",
|
||||
acc_cella_13.synch_mode = "on",
|
||||
acc_cella_13.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_14
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_13cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_14cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[14:14]),
|
||||
.datab(wire_acc_cella_datab[14:14]),
|
||||
.datac(wire_acc_cella_datac[14:14]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[14:14]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_14.cin_used = "true",
|
||||
acc_cella_14.lut_mask = "96e8",
|
||||
acc_cella_14.operation_mode = "arithmetic",
|
||||
acc_cella_14.sum_lutc_input = "cin",
|
||||
acc_cella_14.synch_mode = "on",
|
||||
acc_cella_14.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_15
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_14cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_15cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[15:15]),
|
||||
.datab(wire_acc_cella_datab[15:15]),
|
||||
.datac(wire_acc_cella_datac[15:15]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[15:15]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_15.cin_used = "true",
|
||||
acc_cella_15.lut_mask = "96e8",
|
||||
acc_cella_15.operation_mode = "arithmetic",
|
||||
acc_cella_15.sum_lutc_input = "cin",
|
||||
acc_cella_15.synch_mode = "on",
|
||||
acc_cella_15.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_16
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_15cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_16cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[16:16]),
|
||||
.datab(wire_acc_cella_datab[16:16]),
|
||||
.datac(wire_acc_cella_datac[16:16]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[16:16]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_16.cin_used = "true",
|
||||
acc_cella_16.lut_mask = "96e8",
|
||||
acc_cella_16.operation_mode = "arithmetic",
|
||||
acc_cella_16.sum_lutc_input = "cin",
|
||||
acc_cella_16.synch_mode = "on",
|
||||
acc_cella_16.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_17
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_16cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_17cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[17:17]),
|
||||
.datab(wire_acc_cella_datab[17:17]),
|
||||
.datac(wire_acc_cella_datac[17:17]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[17:17]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_17.cin_used = "true",
|
||||
acc_cella_17.lut_mask = "96e8",
|
||||
acc_cella_17.operation_mode = "arithmetic",
|
||||
acc_cella_17.sum_lutc_input = "cin",
|
||||
acc_cella_17.synch_mode = "on",
|
||||
acc_cella_17.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_18
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_17cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_18cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[18:18]),
|
||||
.datab(wire_acc_cella_datab[18:18]),
|
||||
.datac(wire_acc_cella_datac[18:18]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[18:18]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_18.cin_used = "true",
|
||||
acc_cella_18.lut_mask = "96e8",
|
||||
acc_cella_18.operation_mode = "arithmetic",
|
||||
acc_cella_18.sum_lutc_input = "cin",
|
||||
acc_cella_18.synch_mode = "on",
|
||||
acc_cella_18.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_19
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_18cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_19cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[19:19]),
|
||||
.datab(wire_acc_cella_datab[19:19]),
|
||||
.datac(wire_acc_cella_datac[19:19]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[19:19]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_19.cin_used = "true",
|
||||
acc_cella_19.lut_mask = "96e8",
|
||||
acc_cella_19.operation_mode = "arithmetic",
|
||||
acc_cella_19.sum_lutc_input = "cin",
|
||||
acc_cella_19.synch_mode = "on",
|
||||
acc_cella_19.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_20
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_19cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_20cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[20:20]),
|
||||
.datab(wire_acc_cella_datab[20:20]),
|
||||
.datac(wire_acc_cella_datac[20:20]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[20:20]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_20.cin_used = "true",
|
||||
acc_cella_20.lut_mask = "96e8",
|
||||
acc_cella_20.operation_mode = "arithmetic",
|
||||
acc_cella_20.sum_lutc_input = "cin",
|
||||
acc_cella_20.synch_mode = "on",
|
||||
acc_cella_20.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_21
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_20cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_21cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[21:21]),
|
||||
.datab(wire_acc_cella_datab[21:21]),
|
||||
.datac(wire_acc_cella_datac[21:21]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[21:21]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_21.cin_used = "true",
|
||||
acc_cella_21.lut_mask = "96e8",
|
||||
acc_cella_21.operation_mode = "arithmetic",
|
||||
acc_cella_21.sum_lutc_input = "cin",
|
||||
acc_cella_21.synch_mode = "on",
|
||||
acc_cella_21.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_22
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_21cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_22cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[22:22]),
|
||||
.datab(wire_acc_cella_datab[22:22]),
|
||||
.datac(wire_acc_cella_datac[22:22]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[22:22]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_22.cin_used = "true",
|
||||
acc_cella_22.lut_mask = "96e8",
|
||||
acc_cella_22.operation_mode = "arithmetic",
|
||||
acc_cella_22.sum_lutc_input = "cin",
|
||||
acc_cella_22.synch_mode = "on",
|
||||
acc_cella_22.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_23
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_22cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_23cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[23:23]),
|
||||
.datab(wire_acc_cella_datab[23:23]),
|
||||
.datac(wire_acc_cella_datac[23:23]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[23:23]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_23.cin_used = "true",
|
||||
acc_cella_23.lut_mask = "96e8",
|
||||
acc_cella_23.operation_mode = "arithmetic",
|
||||
acc_cella_23.sum_lutc_input = "cin",
|
||||
acc_cella_23.synch_mode = "on",
|
||||
acc_cella_23.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_24
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_23cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_24cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[24:24]),
|
||||
.datab(wire_acc_cella_datab[24:24]),
|
||||
.datac(wire_acc_cella_datac[24:24]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[24:24]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_24.cin_used = "true",
|
||||
acc_cella_24.lut_mask = "96e8",
|
||||
acc_cella_24.operation_mode = "arithmetic",
|
||||
acc_cella_24.sum_lutc_input = "cin",
|
||||
acc_cella_24.synch_mode = "on",
|
||||
acc_cella_24.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_25
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_24cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_25cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[25:25]),
|
||||
.datab(wire_acc_cella_datab[25:25]),
|
||||
.datac(wire_acc_cella_datac[25:25]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[25:25]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_25.cin_used = "true",
|
||||
acc_cella_25.lut_mask = "96e8",
|
||||
acc_cella_25.operation_mode = "arithmetic",
|
||||
acc_cella_25.sum_lutc_input = "cin",
|
||||
acc_cella_25.synch_mode = "on",
|
||||
acc_cella_25.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_26
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_25cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_26cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[26:26]),
|
||||
.datab(wire_acc_cella_datab[26:26]),
|
||||
.datac(wire_acc_cella_datac[26:26]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[26:26]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_26.cin_used = "true",
|
||||
acc_cella_26.lut_mask = "96e8",
|
||||
acc_cella_26.operation_mode = "arithmetic",
|
||||
acc_cella_26.sum_lutc_input = "cin",
|
||||
acc_cella_26.synch_mode = "on",
|
||||
acc_cella_26.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_27
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_26cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_27cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[27:27]),
|
||||
.datab(wire_acc_cella_datab[27:27]),
|
||||
.datac(wire_acc_cella_datac[27:27]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[27:27]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_27.cin_used = "true",
|
||||
acc_cella_27.lut_mask = "96e8",
|
||||
acc_cella_27.operation_mode = "arithmetic",
|
||||
acc_cella_27.sum_lutc_input = "cin",
|
||||
acc_cella_27.synch_mode = "on",
|
||||
acc_cella_27.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_28
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_27cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_28cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[28:28]),
|
||||
.datab(wire_acc_cella_datab[28:28]),
|
||||
.datac(wire_acc_cella_datac[28:28]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[28:28]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_28.cin_used = "true",
|
||||
acc_cella_28.lut_mask = "96e8",
|
||||
acc_cella_28.operation_mode = "arithmetic",
|
||||
acc_cella_28.sum_lutc_input = "cin",
|
||||
acc_cella_28.synch_mode = "on",
|
||||
acc_cella_28.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_29
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_28cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_29cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[29:29]),
|
||||
.datab(wire_acc_cella_datab[29:29]),
|
||||
.datac(wire_acc_cella_datac[29:29]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[29:29]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_29.cin_used = "true",
|
||||
acc_cella_29.lut_mask = "96e8",
|
||||
acc_cella_29.operation_mode = "arithmetic",
|
||||
acc_cella_29.sum_lutc_input = "cin",
|
||||
acc_cella_29.synch_mode = "on",
|
||||
acc_cella_29.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_30
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_29cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_acc_cella_30cout[0:0]),
|
||||
.dataa(wire_acc_cella_dataa[30:30]),
|
||||
.datab(wire_acc_cella_datab[30:30]),
|
||||
.datac(wire_acc_cella_datac[30:30]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[30:30]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_30.cin_used = "true",
|
||||
acc_cella_30.lut_mask = "96e8",
|
||||
acc_cella_30.operation_mode = "arithmetic",
|
||||
acc_cella_30.sum_lutc_input = "cin",
|
||||
acc_cella_30.synch_mode = "on",
|
||||
acc_cella_30.lpm_type = "stratix_lcell";
|
||||
stratix_lcell acc_cella_31
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_acc_cella_30cout[0:0]),
|
||||
.clk(clock),
|
||||
.dataa(wire_acc_cella_dataa[31:31]),
|
||||
.datab(wire_acc_cella_datab[31:31]),
|
||||
.datac(wire_acc_cella_datac[31:31]),
|
||||
.ena(clken),
|
||||
.regout(wire_acc_cella_regout[31:31]),
|
||||
.sload(sload));
|
||||
defparam
|
||||
acc_cella_31.cin_used = "true",
|
||||
acc_cella_31.lut_mask = "9696",
|
||||
acc_cella_31.operation_mode = "normal",
|
||||
acc_cella_31.sum_lutc_input = "cin",
|
||||
acc_cella_31.synch_mode = "on",
|
||||
acc_cella_31.lpm_type = "stratix_lcell";
|
||||
assign
|
||||
wire_acc_cella_dataa = data,
|
||||
wire_acc_cella_datab = wire_acc_cella_regout,
|
||||
wire_acc_cella_datac = data;
|
||||
assign
|
||||
result = wire_acc_cella_regout,
|
||||
sload = 1'b0;
|
||||
endmodule //accum32_accum_nta
|
||||
//VALID FILE
|
||||
|
||||
|
||||
module accum32 (
|
||||
data,
|
||||
clock,
|
||||
clken,
|
||||
aclr,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [31:0] data;
|
||||
input clock;
|
||||
input clken;
|
||||
input aclr;
|
||||
output [31:0] result;
|
||||
|
||||
wire [31:0] sub_wire0;
|
||||
wire [31:0] result = sub_wire0[31:0];
|
||||
|
||||
accum32_accum_nta accum32_accum_nta_component (
|
||||
.clken (clken),
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.data (data),
|
||||
.result (sub_wire0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CIN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: COUT NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
|
||||
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module accum32 (
|
||||
data,
|
||||
clock,
|
||||
clken,
|
||||
aclr,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [31:0] data;
|
||||
input clock;
|
||||
input clken;
|
||||
input aclr;
|
||||
output [31:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
accum32 accum32_inst (
|
||||
.data ( data_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.clken ( clken_sig ),
|
||||
.aclr ( aclr_sig ),
|
||||
.result ( result_sig )
|
||||
);
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 96)
|
||||
(text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 77 31 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
|
||||
(text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
|
||||
(text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 56)
|
||||
(output)
|
||||
(text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
|
||||
(text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 56)(pt 96 56)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
|
||||
(text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 64 32)(pt 96 40)(line_width 1))
|
||||
(line (pt 96 40)(pt 96 72)(line_width 1))
|
||||
(line (pt 96 72)(pt 64 80)(line_width 1))
|
||||
(line (pt 64 80)(pt 64 32)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component add32
|
||||
PORT
|
||||
(
|
||||
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION add32
|
||||
(
|
||||
dataa[7..0],
|
||||
datab[7..0]
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[7..0]
|
||||
);
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
// megafunction wizard: %LPM_ADD_SUB%CBX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: lpm_add_sub
|
||||
|
||||
// ============================================================
|
||||
// File Name: add32.v
|
||||
// Megafunction Name(s):
|
||||
// lpm_add_sub
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
|
||||
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
|
||||
|
||||
//synthesis_resources = lut 8
|
||||
module add32_add_sub_nq7
|
||||
(
|
||||
dataa,
|
||||
datab,
|
||||
result) /* synthesis synthesis_clearbox=1 */;
|
||||
input [7:0] dataa;
|
||||
input [7:0] datab;
|
||||
output [7:0] result;
|
||||
|
||||
wire [7:0] wire_add_sub_cella_combout;
|
||||
wire [0:0] wire_add_sub_cella_0cout;
|
||||
wire [0:0] wire_add_sub_cella_1cout;
|
||||
wire [0:0] wire_add_sub_cella_2cout;
|
||||
wire [0:0] wire_add_sub_cella_3cout;
|
||||
wire [0:0] wire_add_sub_cella_4cout;
|
||||
wire [0:0] wire_add_sub_cella_5cout;
|
||||
wire [0:0] wire_add_sub_cella_6cout;
|
||||
wire [7:0] wire_add_sub_cella_dataa;
|
||||
wire [7:0] wire_add_sub_cella_datab;
|
||||
|
||||
stratix_lcell add_sub_cella_0
|
||||
(
|
||||
.cin(1'b0),
|
||||
.combout(wire_add_sub_cella_combout[0:0]),
|
||||
.cout(wire_add_sub_cella_0cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[0:0]),
|
||||
.datab(wire_add_sub_cella_datab[0:0]));
|
||||
defparam
|
||||
add_sub_cella_0.cin_used = "true",
|
||||
add_sub_cella_0.lut_mask = "96e8",
|
||||
add_sub_cella_0.operation_mode = "arithmetic",
|
||||
add_sub_cella_0.sum_lutc_input = "cin",
|
||||
add_sub_cella_0.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_1
|
||||
(
|
||||
.cin(wire_add_sub_cella_0cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[1:1]),
|
||||
.cout(wire_add_sub_cella_1cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[1:1]),
|
||||
.datab(wire_add_sub_cella_datab[1:1]));
|
||||
defparam
|
||||
add_sub_cella_1.cin_used = "true",
|
||||
add_sub_cella_1.lut_mask = "96e8",
|
||||
add_sub_cella_1.operation_mode = "arithmetic",
|
||||
add_sub_cella_1.sum_lutc_input = "cin",
|
||||
add_sub_cella_1.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_2
|
||||
(
|
||||
.cin(wire_add_sub_cella_1cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[2:2]),
|
||||
.cout(wire_add_sub_cella_2cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[2:2]),
|
||||
.datab(wire_add_sub_cella_datab[2:2]));
|
||||
defparam
|
||||
add_sub_cella_2.cin_used = "true",
|
||||
add_sub_cella_2.lut_mask = "96e8",
|
||||
add_sub_cella_2.operation_mode = "arithmetic",
|
||||
add_sub_cella_2.sum_lutc_input = "cin",
|
||||
add_sub_cella_2.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_3
|
||||
(
|
||||
.cin(wire_add_sub_cella_2cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[3:3]),
|
||||
.cout(wire_add_sub_cella_3cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[3:3]),
|
||||
.datab(wire_add_sub_cella_datab[3:3]));
|
||||
defparam
|
||||
add_sub_cella_3.cin_used = "true",
|
||||
add_sub_cella_3.lut_mask = "96e8",
|
||||
add_sub_cella_3.operation_mode = "arithmetic",
|
||||
add_sub_cella_3.sum_lutc_input = "cin",
|
||||
add_sub_cella_3.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_4
|
||||
(
|
||||
.cin(wire_add_sub_cella_3cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[4:4]),
|
||||
.cout(wire_add_sub_cella_4cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[4:4]),
|
||||
.datab(wire_add_sub_cella_datab[4:4]));
|
||||
defparam
|
||||
add_sub_cella_4.cin_used = "true",
|
||||
add_sub_cella_4.lut_mask = "96e8",
|
||||
add_sub_cella_4.operation_mode = "arithmetic",
|
||||
add_sub_cella_4.sum_lutc_input = "cin",
|
||||
add_sub_cella_4.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_5
|
||||
(
|
||||
.cin(wire_add_sub_cella_4cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[5:5]),
|
||||
.cout(wire_add_sub_cella_5cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[5:5]),
|
||||
.datab(wire_add_sub_cella_datab[5:5]));
|
||||
defparam
|
||||
add_sub_cella_5.cin_used = "true",
|
||||
add_sub_cella_5.lut_mask = "96e8",
|
||||
add_sub_cella_5.operation_mode = "arithmetic",
|
||||
add_sub_cella_5.sum_lutc_input = "cin",
|
||||
add_sub_cella_5.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_6
|
||||
(
|
||||
.cin(wire_add_sub_cella_5cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[6:6]),
|
||||
.cout(wire_add_sub_cella_6cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[6:6]),
|
||||
.datab(wire_add_sub_cella_datab[6:6]));
|
||||
defparam
|
||||
add_sub_cella_6.cin_used = "true",
|
||||
add_sub_cella_6.lut_mask = "96e8",
|
||||
add_sub_cella_6.operation_mode = "arithmetic",
|
||||
add_sub_cella_6.sum_lutc_input = "cin",
|
||||
add_sub_cella_6.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_7
|
||||
(
|
||||
.cin(wire_add_sub_cella_6cout[0:0]),
|
||||
.combout(wire_add_sub_cella_combout[7:7]),
|
||||
.dataa(wire_add_sub_cella_dataa[7:7]),
|
||||
.datab(wire_add_sub_cella_datab[7:7]));
|
||||
defparam
|
||||
add_sub_cella_7.cin_used = "true",
|
||||
add_sub_cella_7.lut_mask = "9696",
|
||||
add_sub_cella_7.operation_mode = "normal",
|
||||
add_sub_cella_7.sum_lutc_input = "cin",
|
||||
add_sub_cella_7.lpm_type = "stratix_lcell";
|
||||
assign
|
||||
wire_add_sub_cella_dataa = dataa,
|
||||
wire_add_sub_cella_datab = datab;
|
||||
assign
|
||||
result = wire_add_sub_cella_combout;
|
||||
endmodule //add32_add_sub_nq7
|
||||
//VALID FILE
|
||||
|
||||
|
||||
module add32 (
|
||||
dataa,
|
||||
datab,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [7:0] dataa;
|
||||
input [7:0] datab;
|
||||
output [7:0] result;
|
||||
|
||||
wire [7:0] sub_wire0;
|
||||
wire [7:0] result = sub_wire0[7:0];
|
||||
|
||||
add32_add_sub_nq7 add32_add_sub_nq7_component (
|
||||
.dataa (dataa),
|
||||
.datab (datab),
|
||||
.result (sub_wire0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: Function NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
|
||||
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
|
||||
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
|
||||
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
||||
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module add32 (
|
||||
dataa,
|
||||
datab,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [7:0] dataa;
|
||||
input [7:0] datab;
|
||||
output [7:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
add32 add32_inst (
|
||||
.dataa ( dataa_sig ),
|
||||
.datab ( datab_sig ),
|
||||
.result ( result_sig )
|
||||
);
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 144)
|
||||
(text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 125 31 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 88)
|
||||
(input)
|
||||
(text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 88)(pt 64 88)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 64 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8)))
|
||||
(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 80 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 74 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 85 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 96 72)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
|
||||
(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
|
||||
(line (pt 64 48)(pt 96 56)(line_width 1))
|
||||
(line (pt 96 56)(pt 96 88)(line_width 1))
|
||||
(line (pt 96 88)(pt 64 96)(line_width 1))
|
||||
(line (pt 64 96)(pt 64 48)(line_width 1))
|
||||
(line (pt 80 32)(pt 80 52)(line_width 1))
|
||||
(line (pt 106 40)(pt 125 40)(line_width 1))
|
||||
(line (pt 74 112)(pt 74 93)(line_width 1))
|
||||
(line (pt 85 128)(pt 85 90)(line_width 1))
|
||||
(line (pt 64 66)(pt 70 72)(line_width 1))
|
||||
(line (pt 70 72)(pt 64 78)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component addsub16
|
||||
PORT
|
||||
(
|
||||
add_sub : IN STD_LOGIC ;
|
||||
dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
aclr : IN STD_LOGIC ;
|
||||
clken : IN STD_LOGIC ;
|
||||
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION addsub16
|
||||
(
|
||||
add_sub,
|
||||
dataa[15..0],
|
||||
datab[15..0],
|
||||
clock,
|
||||
aclr,
|
||||
clken
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[15..0]
|
||||
);
|
||||
|
|
@ -1,438 +0,0 @@
|
|||
// megafunction wizard: %LPM_ADD_SUB%CBX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: lpm_add_sub
|
||||
|
||||
// ============================================================
|
||||
// File Name: addsub16.v
|
||||
// Megafunction Name(s):
|
||||
// lpm_add_sub
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
|
||||
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
|
||||
|
||||
//synthesis_resources = lut 17
|
||||
module addsub16_add_sub_gp9
|
||||
(
|
||||
aclr,
|
||||
add_sub,
|
||||
clken,
|
||||
clock,
|
||||
dataa,
|
||||
datab,
|
||||
result) /* synthesis synthesis_clearbox=1 */;
|
||||
input aclr;
|
||||
input add_sub;
|
||||
input clken;
|
||||
input clock;
|
||||
input [15:0] dataa;
|
||||
input [15:0] datab;
|
||||
output [15:0] result;
|
||||
|
||||
wire [0:0] wire_add_sub_cella_0cout;
|
||||
wire [0:0] wire_add_sub_cella_1cout;
|
||||
wire [0:0] wire_add_sub_cella_2cout;
|
||||
wire [0:0] wire_add_sub_cella_3cout;
|
||||
wire [0:0] wire_add_sub_cella_4cout;
|
||||
wire [0:0] wire_add_sub_cella_5cout;
|
||||
wire [0:0] wire_add_sub_cella_6cout;
|
||||
wire [0:0] wire_add_sub_cella_7cout;
|
||||
wire [0:0] wire_add_sub_cella_8cout;
|
||||
wire [0:0] wire_add_sub_cella_9cout;
|
||||
wire [0:0] wire_add_sub_cella_10cout;
|
||||
wire [0:0] wire_add_sub_cella_11cout;
|
||||
wire [0:0] wire_add_sub_cella_12cout;
|
||||
wire [0:0] wire_add_sub_cella_13cout;
|
||||
wire [0:0] wire_add_sub_cella_14cout;
|
||||
wire [15:0] wire_add_sub_cella_dataa;
|
||||
wire [15:0] wire_add_sub_cella_datab;
|
||||
wire [15:0] wire_add_sub_cella_regout;
|
||||
wire wire_strx_lcell1_cout;
|
||||
|
||||
stratix_lcell add_sub_cella_0
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_strx_lcell1_cout),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_0cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[0:0]),
|
||||
.datab(wire_add_sub_cella_datab[0:0]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[0:0]));
|
||||
defparam
|
||||
add_sub_cella_0.cin_used = "true",
|
||||
add_sub_cella_0.lut_mask = "96e8",
|
||||
add_sub_cella_0.operation_mode = "arithmetic",
|
||||
add_sub_cella_0.sum_lutc_input = "cin",
|
||||
add_sub_cella_0.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_1
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_0cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_1cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[1:1]),
|
||||
.datab(wire_add_sub_cella_datab[1:1]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[1:1]));
|
||||
defparam
|
||||
add_sub_cella_1.cin_used = "true",
|
||||
add_sub_cella_1.lut_mask = "96e8",
|
||||
add_sub_cella_1.operation_mode = "arithmetic",
|
||||
add_sub_cella_1.sum_lutc_input = "cin",
|
||||
add_sub_cella_1.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_2
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_1cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_2cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[2:2]),
|
||||
.datab(wire_add_sub_cella_datab[2:2]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[2:2]));
|
||||
defparam
|
||||
add_sub_cella_2.cin_used = "true",
|
||||
add_sub_cella_2.lut_mask = "96e8",
|
||||
add_sub_cella_2.operation_mode = "arithmetic",
|
||||
add_sub_cella_2.sum_lutc_input = "cin",
|
||||
add_sub_cella_2.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_3
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_2cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_3cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[3:3]),
|
||||
.datab(wire_add_sub_cella_datab[3:3]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[3:3]));
|
||||
defparam
|
||||
add_sub_cella_3.cin_used = "true",
|
||||
add_sub_cella_3.lut_mask = "96e8",
|
||||
add_sub_cella_3.operation_mode = "arithmetic",
|
||||
add_sub_cella_3.sum_lutc_input = "cin",
|
||||
add_sub_cella_3.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_4
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_3cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_4cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[4:4]),
|
||||
.datab(wire_add_sub_cella_datab[4:4]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[4:4]));
|
||||
defparam
|
||||
add_sub_cella_4.cin_used = "true",
|
||||
add_sub_cella_4.lut_mask = "96e8",
|
||||
add_sub_cella_4.operation_mode = "arithmetic",
|
||||
add_sub_cella_4.sum_lutc_input = "cin",
|
||||
add_sub_cella_4.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_5
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_4cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_5cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[5:5]),
|
||||
.datab(wire_add_sub_cella_datab[5:5]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[5:5]));
|
||||
defparam
|
||||
add_sub_cella_5.cin_used = "true",
|
||||
add_sub_cella_5.lut_mask = "96e8",
|
||||
add_sub_cella_5.operation_mode = "arithmetic",
|
||||
add_sub_cella_5.sum_lutc_input = "cin",
|
||||
add_sub_cella_5.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_6
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_5cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_6cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[6:6]),
|
||||
.datab(wire_add_sub_cella_datab[6:6]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[6:6]));
|
||||
defparam
|
||||
add_sub_cella_6.cin_used = "true",
|
||||
add_sub_cella_6.lut_mask = "96e8",
|
||||
add_sub_cella_6.operation_mode = "arithmetic",
|
||||
add_sub_cella_6.sum_lutc_input = "cin",
|
||||
add_sub_cella_6.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_7
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_6cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_7cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[7:7]),
|
||||
.datab(wire_add_sub_cella_datab[7:7]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[7:7]));
|
||||
defparam
|
||||
add_sub_cella_7.cin_used = "true",
|
||||
add_sub_cella_7.lut_mask = "96e8",
|
||||
add_sub_cella_7.operation_mode = "arithmetic",
|
||||
add_sub_cella_7.sum_lutc_input = "cin",
|
||||
add_sub_cella_7.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_8
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_7cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_8cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[8:8]),
|
||||
.datab(wire_add_sub_cella_datab[8:8]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[8:8]));
|
||||
defparam
|
||||
add_sub_cella_8.cin_used = "true",
|
||||
add_sub_cella_8.lut_mask = "96e8",
|
||||
add_sub_cella_8.operation_mode = "arithmetic",
|
||||
add_sub_cella_8.sum_lutc_input = "cin",
|
||||
add_sub_cella_8.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_9
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_8cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_9cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[9:9]),
|
||||
.datab(wire_add_sub_cella_datab[9:9]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[9:9]));
|
||||
defparam
|
||||
add_sub_cella_9.cin_used = "true",
|
||||
add_sub_cella_9.lut_mask = "96e8",
|
||||
add_sub_cella_9.operation_mode = "arithmetic",
|
||||
add_sub_cella_9.sum_lutc_input = "cin",
|
||||
add_sub_cella_9.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_10
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_9cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_10cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[10:10]),
|
||||
.datab(wire_add_sub_cella_datab[10:10]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[10:10]));
|
||||
defparam
|
||||
add_sub_cella_10.cin_used = "true",
|
||||
add_sub_cella_10.lut_mask = "96e8",
|
||||
add_sub_cella_10.operation_mode = "arithmetic",
|
||||
add_sub_cella_10.sum_lutc_input = "cin",
|
||||
add_sub_cella_10.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_11
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_10cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_11cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[11:11]),
|
||||
.datab(wire_add_sub_cella_datab[11:11]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[11:11]));
|
||||
defparam
|
||||
add_sub_cella_11.cin_used = "true",
|
||||
add_sub_cella_11.lut_mask = "96e8",
|
||||
add_sub_cella_11.operation_mode = "arithmetic",
|
||||
add_sub_cella_11.sum_lutc_input = "cin",
|
||||
add_sub_cella_11.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_12
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_11cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_12cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[12:12]),
|
||||
.datab(wire_add_sub_cella_datab[12:12]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[12:12]));
|
||||
defparam
|
||||
add_sub_cella_12.cin_used = "true",
|
||||
add_sub_cella_12.lut_mask = "96e8",
|
||||
add_sub_cella_12.operation_mode = "arithmetic",
|
||||
add_sub_cella_12.sum_lutc_input = "cin",
|
||||
add_sub_cella_12.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_13
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_12cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_13cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[13:13]),
|
||||
.datab(wire_add_sub_cella_datab[13:13]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[13:13]));
|
||||
defparam
|
||||
add_sub_cella_13.cin_used = "true",
|
||||
add_sub_cella_13.lut_mask = "96e8",
|
||||
add_sub_cella_13.operation_mode = "arithmetic",
|
||||
add_sub_cella_13.sum_lutc_input = "cin",
|
||||
add_sub_cella_13.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_14
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_13cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_14cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[14:14]),
|
||||
.datab(wire_add_sub_cella_datab[14:14]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[14:14]));
|
||||
defparam
|
||||
add_sub_cella_14.cin_used = "true",
|
||||
add_sub_cella_14.lut_mask = "96e8",
|
||||
add_sub_cella_14.operation_mode = "arithmetic",
|
||||
add_sub_cella_14.sum_lutc_input = "cin",
|
||||
add_sub_cella_14.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_15
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_14cout[0:0]),
|
||||
.clk(clock),
|
||||
.dataa(wire_add_sub_cella_dataa[15:15]),
|
||||
.datab(wire_add_sub_cella_datab[15:15]),
|
||||
.ena(clken),
|
||||
.inverta((~ add_sub)),
|
||||
.regout(wire_add_sub_cella_regout[15:15]));
|
||||
defparam
|
||||
add_sub_cella_15.cin_used = "true",
|
||||
add_sub_cella_15.lut_mask = "9696",
|
||||
add_sub_cella_15.operation_mode = "normal",
|
||||
add_sub_cella_15.sum_lutc_input = "cin",
|
||||
add_sub_cella_15.lpm_type = "stratix_lcell";
|
||||
assign
|
||||
wire_add_sub_cella_dataa = datab,
|
||||
wire_add_sub_cella_datab = dataa;
|
||||
stratix_lcell strx_lcell1
|
||||
(
|
||||
.cout(wire_strx_lcell1_cout),
|
||||
.dataa(1'b0),
|
||||
.datab((~ add_sub)),
|
||||
.inverta((~ add_sub)));
|
||||
defparam
|
||||
strx_lcell1.cin_used = "false",
|
||||
strx_lcell1.lut_mask = "00cc",
|
||||
strx_lcell1.operation_mode = "arithmetic",
|
||||
strx_lcell1.lpm_type = "stratix_lcell";
|
||||
assign
|
||||
result = wire_add_sub_cella_regout;
|
||||
endmodule //addsub16_add_sub_gp9
|
||||
//VALID FILE
|
||||
|
||||
|
||||
module addsub16 (
|
||||
add_sub,
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
aclr,
|
||||
clken,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input add_sub;
|
||||
input [15:0] dataa;
|
||||
input [15:0] datab;
|
||||
input clock;
|
||||
input aclr;
|
||||
input clken;
|
||||
output [15:0] result;
|
||||
|
||||
wire [15:0] sub_wire0;
|
||||
wire [15:0] result = sub_wire0[15:0];
|
||||
|
||||
addsub16_add_sub_gp9 addsub16_add_sub_gp9_component (
|
||||
.dataa (dataa),
|
||||
.add_sub (add_sub),
|
||||
.datab (datab),
|
||||
.clken (clken),
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.result (sub_wire0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: Function NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
|
||||
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
|
||||
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
|
||||
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
|
||||
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
|
||||
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module addsub16 (
|
||||
add_sub,
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
aclr,
|
||||
clken,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input add_sub;
|
||||
input [15:0] dataa;
|
||||
input [15:0] datab;
|
||||
input clock;
|
||||
input aclr;
|
||||
input clken;
|
||||
output [15:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
addsub16 addsub16_inst (
|
||||
.add_sub ( add_sub_sig ),
|
||||
.dataa ( dataa_sig ),
|
||||
.datab ( datab_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.aclr ( aclr_sig ),
|
||||
.clken ( clken_sig ),
|
||||
.result ( result_sig )
|
||||
);
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16" (rect 61 25 71 37)(font "Arial" ))
|
||||
(text "16" (rect 13 25 23 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 56 28)(pt 64 20)(line_width 1))
|
||||
(line (pt 8 28)(pt 16 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component bustri
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION bustri
|
||||
(
|
||||
data[15..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[15..0]
|
||||
);
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
// megafunction wizard: %LPM_BUSTRI%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: lpm_bustri
|
||||
|
||||
// ============================================================
|
||||
// File Name: bustri.v
|
||||
// Megafunction Name(s):
|
||||
// lpm_bustri
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
module bustri (
|
||||
data,
|
||||
enabledt,
|
||||
tridata);
|
||||
|
||||
input [15:0] data;
|
||||
input enabledt;
|
||||
inout [15:0] tridata;
|
||||
|
||||
|
||||
lpm_bustri lpm_bustri_component (
|
||||
.tridata (tridata),
|
||||
.enabledt (enabledt),
|
||||
.data (data));
|
||||
defparam
|
||||
lpm_bustri_component.lpm_width = 16,
|
||||
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module bustri (
|
||||
data,
|
||||
enabledt,
|
||||
tridata);
|
||||
|
||||
input [15:0] data;
|
||||
input enabledt;
|
||||
inout [15:0] tridata;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
bustri bustri_inst (
|
||||
.data ( data_sig ),
|
||||
.enabledt ( enabledt_sig ),
|
||||
.tridata ( tridata_sig )
|
||||
);
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: clk_doubler.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 4.2 Build 156 11/29/2004 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module clk_doubler (
|
||||
inclk0,
|
||||
c0);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire [0:0] sub_wire4 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire sub_wire2 = inclk0;
|
||||
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire3),
|
||||
.clk (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.activeclock (),
|
||||
.areset (),
|
||||
.clkbad (),
|
||||
.clkena (),
|
||||
.clkloss (),
|
||||
.clkswitch (),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena (),
|
||||
.fbin (),
|
||||
.locked (),
|
||||
.pfdena (),
|
||||
.pllena (),
|
||||
.scanaclr (),
|
||||
.scanclk (),
|
||||
.scandata (),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (),
|
||||
.scanwrite (),
|
||||
.sclkout0 (),
|
||||
.sclkout1 ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.clk0_multiply_by = 2,
|
||||
altpll_component.inclk0_input_frequency = 15625,
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.intended_device_family = "Cyclone",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.clk0_phase_shift = "0";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
// megafunction wizard: %ALTPLL%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: clk_doubler.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 4.2 Build 156 11/29/2004 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module clk_doubler (
|
||||
inclk0,
|
||||
c0);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
||||
|
|
@ -1,237 +0,0 @@
|
|||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: dspclkpll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module dspclkpll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire [1:1] sub_wire2 = sub_wire0[1:1];
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire c1 = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire4),
|
||||
.clk (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.fbin (),
|
||||
.pllena (),
|
||||
.clkswitch (),
|
||||
.areset (),
|
||||
.pfdena (),
|
||||
.clkena (),
|
||||
.extclkena (),
|
||||
.scanclk (),
|
||||
.scanaclr (),
|
||||
.scandata (),
|
||||
.scanread (),
|
||||
.scanwrite (),
|
||||
.extclk (),
|
||||
.clkbad (),
|
||||
.activeclock (),
|
||||
.locked (),
|
||||
.clkloss (),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.sclkout1 (),
|
||||
.sclkout0 (),
|
||||
.enable0 (),
|
||||
.enable1 ()
|
||||
// synopsys translate_on
|
||||
|
||||
);
|
||||
defparam
|
||||
altpll_component.clk1_divide_by = 1,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.inclk0_input_frequency = 15625,
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.clk1_multiply_by = 2,
|
||||
altpll_component.clk0_time_delay = "0",
|
||||
altpll_component.intended_device_family = "Cyclone",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.clk1_time_delay = "0",
|
||||
altpll_component.clk0_phase_shift = "0";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
|
||||
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module dspclkpll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2006 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 160)
|
||||
(text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 144 25 156)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 32)(pt 144 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 56)
|
||||
(output)
|
||||
(text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||
(text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 56)(pt 144 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
||||
(text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 144 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 88)
|
||||
(output)
|
||||
(text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8)))
|
||||
(text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 88)(pt 144 88)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 104)
|
||||
(output)
|
||||
(text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8)))
|
||||
(text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 104)(pt 144 104)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" ))
|
||||
(text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 144 16)(line_width 1))
|
||||
(line (pt 144 16)(pt 144 144)(line_width 1))
|
||||
(line (pt 144 144)(pt 16 144)(line_width 1))
|
||||
(line (pt 16 144)(pt 16 16)(line_width 1))
|
||||
(line (pt 16 116)(pt 144 116)(line_width 1))
|
||||
(line (pt 16 90)(pt 22 96)(line_width 1))
|
||||
(line (pt 22 96)(pt 16 102)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--Copyright (C) 1991-2006 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component fifo_1kx16
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC ;
|
||||
clock : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
almost_empty : OUT STD_LOGIC ;
|
||||
empty : OUT STD_LOGIC ;
|
||||
full : OUT STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--Copyright (C) 1991-2006 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION fifo_1kx16
|
||||
(
|
||||
aclr,
|
||||
clock,
|
||||
data[15..0],
|
||||
rdreq,
|
||||
wrreq
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
almost_empty,
|
||||
empty,
|
||||
full,
|
||||
q[15..0],
|
||||
usedw[9..0]
|
||||
);
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: scfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_1kx16.v
|
||||
// Megafunction Name(s):
|
||||
// scfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2006 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module fifo_1kx16 (
|
||||
aclr,
|
||||
clock,
|
||||
data,
|
||||
rdreq,
|
||||
wrreq,
|
||||
almost_empty,
|
||||
empty,
|
||||
full,
|
||||
q,
|
||||
usedw);
|
||||
|
||||
input aclr;
|
||||
input clock;
|
||||
input [15:0] data;
|
||||
input rdreq;
|
||||
input wrreq;
|
||||
output almost_empty;
|
||||
output empty;
|
||||
output full;
|
||||
output [15:0] q;
|
||||
output [9:0] usedw;
|
||||
|
||||
wire [9:0] sub_wire0;
|
||||
wire sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire [15:0] sub_wire3;
|
||||
wire sub_wire4;
|
||||
wire [9:0] usedw = sub_wire0[9:0];
|
||||
wire empty = sub_wire1;
|
||||
wire almost_empty = sub_wire2;
|
||||
wire [15:0] q = sub_wire3[15:0];
|
||||
wire full = sub_wire4;
|
||||
|
||||
scfifo scfifo_component (
|
||||
.rdreq (rdreq),
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.wrreq (wrreq),
|
||||
.data (data),
|
||||
.usedw (sub_wire0),
|
||||
.empty (sub_wire1),
|
||||
.almost_empty (sub_wire2),
|
||||
.q (sub_wire3),
|
||||
.full (sub_wire4)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.sclr (),
|
||||
.almost_full ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
scfifo_component.add_ram_output_register = "OFF",
|
||||
scfifo_component.almost_empty_value = 504,
|
||||
scfifo_component.intended_device_family = "Cyclone",
|
||||
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
|
||||
scfifo_component.lpm_numwords = 1024,
|
||||
scfifo_component.lpm_showahead = "OFF",
|
||||
scfifo_component.lpm_type = "scfifo",
|
||||
scfifo_component.lpm_width = 16,
|
||||
scfifo_component.lpm_widthu = 10,
|
||||
scfifo_component.overflow_checking = "ON",
|
||||
scfifo_component.underflow_checking = "ON",
|
||||
scfifo_component.use_eab = "ON";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
||||
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
|
||||
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
|
||||
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
|
||||
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
// megafunction wizard: %FIFO%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: scfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_1kx16.v
|
||||
// Megafunction Name(s):
|
||||
// scfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2006 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module fifo_1kx16 (
|
||||
aclr,
|
||||
clock,
|
||||
data,
|
||||
rdreq,
|
||||
wrreq,
|
||||
almost_empty,
|
||||
empty,
|
||||
full,
|
||||
q,
|
||||
usedw);
|
||||
|
||||
input aclr;
|
||||
input clock;
|
||||
input [15:0] data;
|
||||
input rdreq;
|
||||
input wrreq;
|
||||
output almost_empty;
|
||||
output empty;
|
||||
output full;
|
||||
output [15:0] q;
|
||||
output [9:0] usedw;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
||||
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
|
||||
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
|
||||
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
|
||||
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
fifo_1kx16 fifo_1kx16_inst (
|
||||
.aclr ( aclr_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.data ( data_sig ),
|
||||
.rdreq ( rdreq_sig ),
|
||||
.wrreq ( wrreq_sig ),
|
||||
.almost_empty ( almost_empty_sig ),
|
||||
.empty ( empty_sig ),
|
||||
.full ( full_sig ),
|
||||
.q ( q_sig ),
|
||||
.usedw ( usedw_sig )
|
||||
);
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,131 +0,0 @@
|
|||
// megafunction wizard: %FIFO%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_2k.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2005 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module fifo_2k (
|
||||
data,
|
||||
wrreq,
|
||||
rdreq,
|
||||
rdclk,
|
||||
wrclk,
|
||||
aclr,
|
||||
q,
|
||||
rdempty,
|
||||
rdusedw,
|
||||
wrfull,
|
||||
wrusedw)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [15:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [15:0] q;
|
||||
output rdempty;
|
||||
output [10:0] rdusedw;
|
||||
output wrfull;
|
||||
output [10:0] wrusedw;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,186 +0,0 @@
|
|||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_4k_18.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2007 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module fifo_4k_18 (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
rdusedw,
|
||||
wrfull,
|
||||
wrusedw);
|
||||
|
||||
input aclr;
|
||||
input [17:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [17:0] q;
|
||||
output rdempty;
|
||||
output [11:0] rdusedw;
|
||||
output wrfull;
|
||||
output [11:0] wrusedw;
|
||||
|
||||
wire sub_wire0;
|
||||
wire [11:0] sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire [17:0] sub_wire3;
|
||||
wire [11:0] sub_wire4;
|
||||
wire rdempty = sub_wire0;
|
||||
wire [11:0] wrusedw = sub_wire1[11:0];
|
||||
wire wrfull = sub_wire2;
|
||||
wire [17:0] q = sub_wire3[17:0];
|
||||
wire [11:0] rdusedw = sub_wire4[11:0];
|
||||
|
||||
dcfifo dcfifo_component (
|
||||
.wrclk (wrclk),
|
||||
.rdreq (rdreq),
|
||||
.aclr (aclr),
|
||||
.rdclk (rdclk),
|
||||
.wrreq (wrreq),
|
||||
.data (data),
|
||||
.rdempty (sub_wire0),
|
||||
.wrusedw (sub_wire1),
|
||||
.wrfull (sub_wire2),
|
||||
.q (sub_wire3),
|
||||
.rdusedw (sub_wire4)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.rdfull (),
|
||||
.wrempty ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
dcfifo_component.add_ram_output_register = "OFF",
|
||||
dcfifo_component.clocks_are_synchronized = "FALSE",
|
||||
dcfifo_component.intended_device_family = "Cyclone",
|
||||
dcfifo_component.lpm_numwords = 4096,
|
||||
dcfifo_component.lpm_showahead = "ON",
|
||||
dcfifo_component.lpm_type = "dcfifo",
|
||||
dcfifo_component.lpm_width = 18,
|
||||
dcfifo_component.lpm_widthu = 12,
|
||||
dcfifo_component.overflow_checking = "OFF",
|
||||
dcfifo_component.underflow_checking = "OFF",
|
||||
dcfifo_component.use_eab = "ON";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "18"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "18"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
|
||||
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
|
||||
// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
|
||||
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
// megafunction wizard: %FIFO%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_4k.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2005 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module fifo_4k (
|
||||
data,
|
||||
wrreq,
|
||||
rdreq,
|
||||
rdclk,
|
||||
wrclk,
|
||||
aclr,
|
||||
q,
|
||||
rdempty,
|
||||
rdusedw,
|
||||
wrfull,
|
||||
wrusedw)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [15:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [15:0] q;
|
||||
output rdempty;
|
||||
output [11:0] rdusedw;
|
||||
output wrfull;
|
||||
output [11:0] wrusedw;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
||||
|
|
@ -1,117 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2006 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 184)
|
||||
(text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 168 25 180)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 16 104)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
|
||||
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 16 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 40)
|
||||
(output)
|
||||
(text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
|
||||
(text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 40)(pt 144 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
|
||||
(text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 144 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 96)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 96)(pt 144 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 120)
|
||||
(output)
|
||||
(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
|
||||
(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 120)(pt 144 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 136)
|
||||
(output)
|
||||
(text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
|
||||
(text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 136)(pt 144 136)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "(ack)" (rect 51 99 72 111)(font "Arial" ))
|
||||
(text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 144 16)(line_width 1))
|
||||
(line (pt 144 16)(pt 144 168)(line_width 1))
|
||||
(line (pt 144 168)(pt 16 168)(line_width 1))
|
||||
(line (pt 16 168)(pt 16 16)(line_width 1))
|
||||
(line (pt 16 84)(pt 144 84)(line_width 1))
|
||||
(line (pt 16 148)(pt 144 148)(line_width 1))
|
||||
(line (pt 16 66)(pt 22 72)(line_width 1))
|
||||
(line (pt 22 72)(pt 16 78)(line_width 1))
|
||||
(line (pt 16 114)(pt 22 120)(line_width 1))
|
||||
(line (pt 22 120)(pt 16 126)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--Copyright (C) 1991-2006 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component fifo_4kx16_dc
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
rdclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
rdempty : OUT STD_LOGIC ;
|
||||
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
|
||||
wrfull : OUT STD_LOGIC ;
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--Copyright (C) 1991-2006 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION fifo_4kx16_dc
|
||||
(
|
||||
aclr,
|
||||
data[15..0],
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
q[15..0],
|
||||
rdempty,
|
||||
rdusedw[11..0],
|
||||
wrfull,
|
||||
wrusedw[11..0]
|
||||
);
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_4kx16_dc.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2006 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module fifo_4kx16_dc (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
rdusedw,
|
||||
wrfull,
|
||||
wrusedw);
|
||||
|
||||
input aclr;
|
||||
input [15:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [15:0] q;
|
||||
output rdempty;
|
||||
output [11:0] rdusedw;
|
||||
output wrfull;
|
||||
output [11:0] wrusedw;
|
||||
|
||||
wire sub_wire0;
|
||||
wire [11:0] sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire [15:0] sub_wire3;
|
||||
wire [11:0] sub_wire4;
|
||||
wire rdempty = sub_wire0;
|
||||
wire [11:0] wrusedw = sub_wire1[11:0];
|
||||
wire wrfull = sub_wire2;
|
||||
wire [15:0] q = sub_wire3[15:0];
|
||||
wire [11:0] rdusedw = sub_wire4[11:0];
|
||||
|
||||
dcfifo dcfifo_component (
|
||||
.wrclk (wrclk),
|
||||
.rdreq (rdreq),
|
||||
.aclr (aclr),
|
||||
.rdclk (rdclk),
|
||||
.wrreq (wrreq),
|
||||
.data (data),
|
||||
.rdempty (sub_wire0),
|
||||
.wrusedw (sub_wire1),
|
||||
.wrfull (sub_wire2),
|
||||
.q (sub_wire3),
|
||||
.rdusedw (sub_wire4)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.wrempty (),
|
||||
.rdfull ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
dcfifo_component.add_ram_output_register = "OFF",
|
||||
dcfifo_component.clocks_are_synchronized = "FALSE",
|
||||
dcfifo_component.intended_device_family = "Cyclone",
|
||||
dcfifo_component.lpm_numwords = 4096,
|
||||
dcfifo_component.lpm_showahead = "ON",
|
||||
dcfifo_component.lpm_type = "dcfifo",
|
||||
dcfifo_component.lpm_width = 16,
|
||||
dcfifo_component.lpm_widthu = 12,
|
||||
dcfifo_component.overflow_checking = "OFF",
|
||||
dcfifo_component.underflow_checking = "OFF",
|
||||
dcfifo_component.use_eab = "ON";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
// megafunction wizard: %FIFO%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: fifo_4kx16_dc.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2006 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module fifo_4kx16_dc (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
rdusedw,
|
||||
wrfull,
|
||||
wrusedw);
|
||||
|
||||
input aclr;
|
||||
input [15:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [15:0] q;
|
||||
output rdempty;
|
||||
output [11:0] rdusedw;
|
||||
output wrfull;
|
||||
output [11:0] wrusedw;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
fifo_4kx16_dc fifo_4kx16_dc_inst (
|
||||
.aclr ( aclr_sig ),
|
||||
.data ( data_sig ),
|
||||
.rdclk ( rdclk_sig ),
|
||||
.rdreq ( rdreq_sig ),
|
||||
.wrclk ( wrclk_sig ),
|
||||
.wrreq ( wrreq_sig ),
|
||||
.q ( q_sig ),
|
||||
.rdempty ( rdempty_sig ),
|
||||
.rdusedw ( rdusedw_sig ),
|
||||
.wrfull ( wrfull_sig ),
|
||||
.wrusedw ( wrusedw_sig )
|
||||
);
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 112)
|
||||
(text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 93 30 108)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
|
||||
(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 88)
|
||||
(input)
|
||||
(text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
|
||||
(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 88)(pt 64 88)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 64 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8)))
|
||||
(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 80 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
|
||||
(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 96 72)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
|
||||
(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
|
||||
(line (pt 64 48)(pt 96 56)(line_width 1))
|
||||
(line (pt 96 56)(pt 96 88)(line_width 1))
|
||||
(line (pt 96 88)(pt 64 96)(line_width 1))
|
||||
(line (pt 64 96)(pt 64 48)(line_width 1))
|
||||
(line (pt 80 32)(pt 80 52)(line_width 1))
|
||||
(line (pt 106 40)(pt 125 40)(line_width 1))
|
||||
(line (pt 64 66)(pt 70 72)(line_width 1))
|
||||
(line (pt 70 72)(pt 64 78)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component mylpm_addsub
|
||||
PORT
|
||||
(
|
||||
add_sub : IN STD_LOGIC ;
|
||||
dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION mylpm_addsub
|
||||
(
|
||||
add_sub,
|
||||
dataa[15..0],
|
||||
datab[15..0],
|
||||
clock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[15..0]
|
||||
);
|
||||
|
|
@ -1,102 +0,0 @@
|
|||
// megafunction wizard: %LPM_ADD_SUB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: lpm_add_sub
|
||||
|
||||
// ============================================================
|
||||
// File Name: mylpm_addsub.v
|
||||
// Megafunction Name(s):
|
||||
// lpm_add_sub
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
module mylpm_addsub (
|
||||
add_sub,
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
result);
|
||||
|
||||
input add_sub;
|
||||
input [15:0] dataa;
|
||||
input [15:0] datab;
|
||||
input clock;
|
||||
output [15:0] result;
|
||||
|
||||
wire [15:0] sub_wire0;
|
||||
wire [15:0] result = sub_wire0[15:0];
|
||||
|
||||
lpm_add_sub lpm_add_sub_component (
|
||||
.dataa (dataa),
|
||||
.add_sub (add_sub),
|
||||
.datab (datab),
|
||||
.clock (clock),
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
lpm_add_sub_component.lpm_width = 16,
|
||||
lpm_add_sub_component.lpm_direction = "UNUSED",
|
||||
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
|
||||
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
|
||||
lpm_add_sub_component.lpm_pipeline = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: Function NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
|
||||
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
|
||||
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
|
||||
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
||||
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
|
||||
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module mylpm_addsub (
|
||||
add_sub,
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
result);
|
||||
|
||||
input add_sub;
|
||||
input [15:0] dataa;
|
||||
input [15:0] datab;
|
||||
input clock;
|
||||
output [15:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
mylpm_addsub mylpm_addsub_inst (
|
||||
.add_sub ( add_sub_sig ),
|
||||
.dataa ( dataa_sig ),
|
||||
.datab ( datab_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.result ( result_sig )
|
||||
);
|
||||
|
|
@ -1,207 +0,0 @@
|
|||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire [0:0] sub_wire4 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire sub_wire2 = inclk0;
|
||||
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire3),
|
||||
.clk (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.fbin (),
|
||||
.pllena (),
|
||||
.clkswitch (),
|
||||
.areset (),
|
||||
.pfdena (),
|
||||
.clkena (),
|
||||
.extclkena (),
|
||||
.scanclk (),
|
||||
.scanaclr (),
|
||||
.scandata (),
|
||||
.scanread (),
|
||||
.scanwrite (),
|
||||
.extclk (),
|
||||
.clkbad (),
|
||||
.activeclock (),
|
||||
.locked (),
|
||||
.clkloss (),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.sclkout1 (),
|
||||
.sclkout0 (),
|
||||
.enable0 (),
|
||||
.enable1 ()
|
||||
// synopsys translate_on
|
||||
|
||||
);
|
||||
defparam
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.inclk0_input_frequency = 20833,
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.clk0_time_delay = "0",
|
||||
altpll_component.intended_device_family = "Cyclone",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.clk0_phase_shift = "-3000";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
|
||||
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
//Copyright (C) 1991-2004 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module pll (
|
||||
inclk0,
|
||||
c0);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
pll pll_inst (
|
||||
.inclk0 ( inclk0_sig ),
|
||||
.c0 ( c0_sig )
|
||||
);
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2003 Altera Corporation
|
||||
Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only
|
||||
to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
other use of such megafunction design, netlist, support information,
|
||||
device programming or simulation file, or any other related documentation
|
||||
or information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to the
|
||||
intellectual property, including patents, copyrights, trademarks, trade
|
||||
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
support information, device programming or simulation file, or any other
|
||||
related documentation or information provided by Altera or a megafunction
|
||||
partner, remains with Altera, the megafunction partner, or their respective
|
||||
licensors. No other licenses, including any licenses needed under any third
|
||||
party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 128)
|
||||
(text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 109 31 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 64 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 74 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 85 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 56)
|
||||
(output)
|
||||
(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 56)(pt 96 56)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
|
||||
(text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 64 32)(pt 96 40)(line_width 1))
|
||||
(line (pt 96 40)(pt 96 72)(line_width 1))
|
||||
(line (pt 96 72)(pt 64 80)(line_width 1))
|
||||
(line (pt 64 80)(pt 64 32)(line_width 1))
|
||||
(line (pt 74 96)(pt 74 77)(line_width 1))
|
||||
(line (pt 85 112)(pt 85 74)(line_width 1))
|
||||
(line (pt 64 50)(pt 70 56)(line_width 1))
|
||||
(line (pt 70 56)(pt 64 62)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
component sub32
|
||||
PORT
|
||||
(
|
||||
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
aclr : IN STD_LOGIC ;
|
||||
clken : IN STD_LOGIC ;
|
||||
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
--Copyright (C) 1991-2003 Altera Corporation
|
||||
--Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
--support information, device programming or simulation file, and any other
|
||||
--associated documentation or information provided by Altera or a partner
|
||||
--under Altera's Megafunction Partnership Program may be used only
|
||||
--to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
--other use of such megafunction design, netlist, support information,
|
||||
--device programming or simulation file, or any other related documentation
|
||||
--or information is prohibited for any other purpose, including, but not
|
||||
--limited to modification, reverse engineering, de-compiling, or use with
|
||||
--any other silicon devices, unless such use is explicitly licensed under
|
||||
--a separate agreement with Altera or a megafunction partner. Title to the
|
||||
--intellectual property, including patents, copyrights, trademarks, trade
|
||||
--secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
--support information, device programming or simulation file, or any other
|
||||
--related documentation or information provided by Altera or a megafunction
|
||||
--partner, remains with Altera, the megafunction partner, or their respective
|
||||
--licensors. No other licenses, including any licenses needed under any third
|
||||
--party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
FUNCTION sub32
|
||||
(
|
||||
dataa[31..0],
|
||||
datab[31..0],
|
||||
clock,
|
||||
aclr,
|
||||
clken
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[31..0]
|
||||
);
|
||||
|
|
@ -1,675 +0,0 @@
|
|||
// megafunction wizard: %LPM_ADD_SUB%CBX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: lpm_add_sub
|
||||
|
||||
// ============================================================
|
||||
// File Name: sub32.v
|
||||
// Megafunction Name(s):
|
||||
// lpm_add_sub
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
|
||||
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
|
||||
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
|
||||
|
||||
//synthesis_resources = lut 32
|
||||
module sub32_add_sub_cqa
|
||||
(
|
||||
aclr,
|
||||
clken,
|
||||
clock,
|
||||
dataa,
|
||||
datab,
|
||||
result) /* synthesis synthesis_clearbox=1 */;
|
||||
input aclr;
|
||||
input clken;
|
||||
input clock;
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
output [31:0] result;
|
||||
|
||||
wire [0:0] wire_add_sub_cella_0cout;
|
||||
wire [0:0] wire_add_sub_cella_1cout;
|
||||
wire [0:0] wire_add_sub_cella_2cout;
|
||||
wire [0:0] wire_add_sub_cella_3cout;
|
||||
wire [0:0] wire_add_sub_cella_4cout;
|
||||
wire [0:0] wire_add_sub_cella_5cout;
|
||||
wire [0:0] wire_add_sub_cella_6cout;
|
||||
wire [0:0] wire_add_sub_cella_7cout;
|
||||
wire [0:0] wire_add_sub_cella_8cout;
|
||||
wire [0:0] wire_add_sub_cella_9cout;
|
||||
wire [0:0] wire_add_sub_cella_10cout;
|
||||
wire [0:0] wire_add_sub_cella_11cout;
|
||||
wire [0:0] wire_add_sub_cella_12cout;
|
||||
wire [0:0] wire_add_sub_cella_13cout;
|
||||
wire [0:0] wire_add_sub_cella_14cout;
|
||||
wire [0:0] wire_add_sub_cella_15cout;
|
||||
wire [0:0] wire_add_sub_cella_16cout;
|
||||
wire [0:0] wire_add_sub_cella_17cout;
|
||||
wire [0:0] wire_add_sub_cella_18cout;
|
||||
wire [0:0] wire_add_sub_cella_19cout;
|
||||
wire [0:0] wire_add_sub_cella_20cout;
|
||||
wire [0:0] wire_add_sub_cella_21cout;
|
||||
wire [0:0] wire_add_sub_cella_22cout;
|
||||
wire [0:0] wire_add_sub_cella_23cout;
|
||||
wire [0:0] wire_add_sub_cella_24cout;
|
||||
wire [0:0] wire_add_sub_cella_25cout;
|
||||
wire [0:0] wire_add_sub_cella_26cout;
|
||||
wire [0:0] wire_add_sub_cella_27cout;
|
||||
wire [0:0] wire_add_sub_cella_28cout;
|
||||
wire [0:0] wire_add_sub_cella_29cout;
|
||||
wire [0:0] wire_add_sub_cella_30cout;
|
||||
wire [31:0] wire_add_sub_cella_dataa;
|
||||
wire [31:0] wire_add_sub_cella_datab;
|
||||
wire [31:0] wire_add_sub_cella_regout;
|
||||
|
||||
stratix_lcell add_sub_cella_0
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(1'b1),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_0cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[0:0]),
|
||||
.datab(wire_add_sub_cella_datab[0:0]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[0:0]));
|
||||
defparam
|
||||
add_sub_cella_0.cin_used = "true",
|
||||
add_sub_cella_0.lut_mask = "69b2",
|
||||
add_sub_cella_0.operation_mode = "arithmetic",
|
||||
add_sub_cella_0.sum_lutc_input = "cin",
|
||||
add_sub_cella_0.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_1
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_0cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_1cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[1:1]),
|
||||
.datab(wire_add_sub_cella_datab[1:1]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[1:1]));
|
||||
defparam
|
||||
add_sub_cella_1.cin_used = "true",
|
||||
add_sub_cella_1.lut_mask = "69b2",
|
||||
add_sub_cella_1.operation_mode = "arithmetic",
|
||||
add_sub_cella_1.sum_lutc_input = "cin",
|
||||
add_sub_cella_1.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_2
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_1cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_2cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[2:2]),
|
||||
.datab(wire_add_sub_cella_datab[2:2]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[2:2]));
|
||||
defparam
|
||||
add_sub_cella_2.cin_used = "true",
|
||||
add_sub_cella_2.lut_mask = "69b2",
|
||||
add_sub_cella_2.operation_mode = "arithmetic",
|
||||
add_sub_cella_2.sum_lutc_input = "cin",
|
||||
add_sub_cella_2.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_3
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_2cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_3cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[3:3]),
|
||||
.datab(wire_add_sub_cella_datab[3:3]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[3:3]));
|
||||
defparam
|
||||
add_sub_cella_3.cin_used = "true",
|
||||
add_sub_cella_3.lut_mask = "69b2",
|
||||
add_sub_cella_3.operation_mode = "arithmetic",
|
||||
add_sub_cella_3.sum_lutc_input = "cin",
|
||||
add_sub_cella_3.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_4
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_3cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_4cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[4:4]),
|
||||
.datab(wire_add_sub_cella_datab[4:4]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[4:4]));
|
||||
defparam
|
||||
add_sub_cella_4.cin_used = "true",
|
||||
add_sub_cella_4.lut_mask = "69b2",
|
||||
add_sub_cella_4.operation_mode = "arithmetic",
|
||||
add_sub_cella_4.sum_lutc_input = "cin",
|
||||
add_sub_cella_4.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_5
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_4cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_5cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[5:5]),
|
||||
.datab(wire_add_sub_cella_datab[5:5]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[5:5]));
|
||||
defparam
|
||||
add_sub_cella_5.cin_used = "true",
|
||||
add_sub_cella_5.lut_mask = "69b2",
|
||||
add_sub_cella_5.operation_mode = "arithmetic",
|
||||
add_sub_cella_5.sum_lutc_input = "cin",
|
||||
add_sub_cella_5.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_6
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_5cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_6cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[6:6]),
|
||||
.datab(wire_add_sub_cella_datab[6:6]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[6:6]));
|
||||
defparam
|
||||
add_sub_cella_6.cin_used = "true",
|
||||
add_sub_cella_6.lut_mask = "69b2",
|
||||
add_sub_cella_6.operation_mode = "arithmetic",
|
||||
add_sub_cella_6.sum_lutc_input = "cin",
|
||||
add_sub_cella_6.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_7
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_6cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_7cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[7:7]),
|
||||
.datab(wire_add_sub_cella_datab[7:7]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[7:7]));
|
||||
defparam
|
||||
add_sub_cella_7.cin_used = "true",
|
||||
add_sub_cella_7.lut_mask = "69b2",
|
||||
add_sub_cella_7.operation_mode = "arithmetic",
|
||||
add_sub_cella_7.sum_lutc_input = "cin",
|
||||
add_sub_cella_7.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_8
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_7cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_8cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[8:8]),
|
||||
.datab(wire_add_sub_cella_datab[8:8]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[8:8]));
|
||||
defparam
|
||||
add_sub_cella_8.cin_used = "true",
|
||||
add_sub_cella_8.lut_mask = "69b2",
|
||||
add_sub_cella_8.operation_mode = "arithmetic",
|
||||
add_sub_cella_8.sum_lutc_input = "cin",
|
||||
add_sub_cella_8.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_9
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_8cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_9cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[9:9]),
|
||||
.datab(wire_add_sub_cella_datab[9:9]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[9:9]));
|
||||
defparam
|
||||
add_sub_cella_9.cin_used = "true",
|
||||
add_sub_cella_9.lut_mask = "69b2",
|
||||
add_sub_cella_9.operation_mode = "arithmetic",
|
||||
add_sub_cella_9.sum_lutc_input = "cin",
|
||||
add_sub_cella_9.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_10
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_9cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_10cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[10:10]),
|
||||
.datab(wire_add_sub_cella_datab[10:10]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[10:10]));
|
||||
defparam
|
||||
add_sub_cella_10.cin_used = "true",
|
||||
add_sub_cella_10.lut_mask = "69b2",
|
||||
add_sub_cella_10.operation_mode = "arithmetic",
|
||||
add_sub_cella_10.sum_lutc_input = "cin",
|
||||
add_sub_cella_10.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_11
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_10cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_11cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[11:11]),
|
||||
.datab(wire_add_sub_cella_datab[11:11]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[11:11]));
|
||||
defparam
|
||||
add_sub_cella_11.cin_used = "true",
|
||||
add_sub_cella_11.lut_mask = "69b2",
|
||||
add_sub_cella_11.operation_mode = "arithmetic",
|
||||
add_sub_cella_11.sum_lutc_input = "cin",
|
||||
add_sub_cella_11.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_12
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_11cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_12cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[12:12]),
|
||||
.datab(wire_add_sub_cella_datab[12:12]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[12:12]));
|
||||
defparam
|
||||
add_sub_cella_12.cin_used = "true",
|
||||
add_sub_cella_12.lut_mask = "69b2",
|
||||
add_sub_cella_12.operation_mode = "arithmetic",
|
||||
add_sub_cella_12.sum_lutc_input = "cin",
|
||||
add_sub_cella_12.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_13
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_12cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_13cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[13:13]),
|
||||
.datab(wire_add_sub_cella_datab[13:13]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[13:13]));
|
||||
defparam
|
||||
add_sub_cella_13.cin_used = "true",
|
||||
add_sub_cella_13.lut_mask = "69b2",
|
||||
add_sub_cella_13.operation_mode = "arithmetic",
|
||||
add_sub_cella_13.sum_lutc_input = "cin",
|
||||
add_sub_cella_13.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_14
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_13cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_14cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[14:14]),
|
||||
.datab(wire_add_sub_cella_datab[14:14]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[14:14]));
|
||||
defparam
|
||||
add_sub_cella_14.cin_used = "true",
|
||||
add_sub_cella_14.lut_mask = "69b2",
|
||||
add_sub_cella_14.operation_mode = "arithmetic",
|
||||
add_sub_cella_14.sum_lutc_input = "cin",
|
||||
add_sub_cella_14.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_15
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_14cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_15cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[15:15]),
|
||||
.datab(wire_add_sub_cella_datab[15:15]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[15:15]));
|
||||
defparam
|
||||
add_sub_cella_15.cin_used = "true",
|
||||
add_sub_cella_15.lut_mask = "69b2",
|
||||
add_sub_cella_15.operation_mode = "arithmetic",
|
||||
add_sub_cella_15.sum_lutc_input = "cin",
|
||||
add_sub_cella_15.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_16
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_15cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_16cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[16:16]),
|
||||
.datab(wire_add_sub_cella_datab[16:16]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[16:16]));
|
||||
defparam
|
||||
add_sub_cella_16.cin_used = "true",
|
||||
add_sub_cella_16.lut_mask = "69b2",
|
||||
add_sub_cella_16.operation_mode = "arithmetic",
|
||||
add_sub_cella_16.sum_lutc_input = "cin",
|
||||
add_sub_cella_16.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_17
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_16cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_17cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[17:17]),
|
||||
.datab(wire_add_sub_cella_datab[17:17]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[17:17]));
|
||||
defparam
|
||||
add_sub_cella_17.cin_used = "true",
|
||||
add_sub_cella_17.lut_mask = "69b2",
|
||||
add_sub_cella_17.operation_mode = "arithmetic",
|
||||
add_sub_cella_17.sum_lutc_input = "cin",
|
||||
add_sub_cella_17.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_18
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_17cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_18cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[18:18]),
|
||||
.datab(wire_add_sub_cella_datab[18:18]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[18:18]));
|
||||
defparam
|
||||
add_sub_cella_18.cin_used = "true",
|
||||
add_sub_cella_18.lut_mask = "69b2",
|
||||
add_sub_cella_18.operation_mode = "arithmetic",
|
||||
add_sub_cella_18.sum_lutc_input = "cin",
|
||||
add_sub_cella_18.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_19
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_18cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_19cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[19:19]),
|
||||
.datab(wire_add_sub_cella_datab[19:19]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[19:19]));
|
||||
defparam
|
||||
add_sub_cella_19.cin_used = "true",
|
||||
add_sub_cella_19.lut_mask = "69b2",
|
||||
add_sub_cella_19.operation_mode = "arithmetic",
|
||||
add_sub_cella_19.sum_lutc_input = "cin",
|
||||
add_sub_cella_19.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_20
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_19cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_20cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[20:20]),
|
||||
.datab(wire_add_sub_cella_datab[20:20]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[20:20]));
|
||||
defparam
|
||||
add_sub_cella_20.cin_used = "true",
|
||||
add_sub_cella_20.lut_mask = "69b2",
|
||||
add_sub_cella_20.operation_mode = "arithmetic",
|
||||
add_sub_cella_20.sum_lutc_input = "cin",
|
||||
add_sub_cella_20.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_21
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_20cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_21cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[21:21]),
|
||||
.datab(wire_add_sub_cella_datab[21:21]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[21:21]));
|
||||
defparam
|
||||
add_sub_cella_21.cin_used = "true",
|
||||
add_sub_cella_21.lut_mask = "69b2",
|
||||
add_sub_cella_21.operation_mode = "arithmetic",
|
||||
add_sub_cella_21.sum_lutc_input = "cin",
|
||||
add_sub_cella_21.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_22
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_21cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_22cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[22:22]),
|
||||
.datab(wire_add_sub_cella_datab[22:22]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[22:22]));
|
||||
defparam
|
||||
add_sub_cella_22.cin_used = "true",
|
||||
add_sub_cella_22.lut_mask = "69b2",
|
||||
add_sub_cella_22.operation_mode = "arithmetic",
|
||||
add_sub_cella_22.sum_lutc_input = "cin",
|
||||
add_sub_cella_22.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_23
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_22cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_23cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[23:23]),
|
||||
.datab(wire_add_sub_cella_datab[23:23]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[23:23]));
|
||||
defparam
|
||||
add_sub_cella_23.cin_used = "true",
|
||||
add_sub_cella_23.lut_mask = "69b2",
|
||||
add_sub_cella_23.operation_mode = "arithmetic",
|
||||
add_sub_cella_23.sum_lutc_input = "cin",
|
||||
add_sub_cella_23.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_24
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_23cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_24cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[24:24]),
|
||||
.datab(wire_add_sub_cella_datab[24:24]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[24:24]));
|
||||
defparam
|
||||
add_sub_cella_24.cin_used = "true",
|
||||
add_sub_cella_24.lut_mask = "69b2",
|
||||
add_sub_cella_24.operation_mode = "arithmetic",
|
||||
add_sub_cella_24.sum_lutc_input = "cin",
|
||||
add_sub_cella_24.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_25
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_24cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_25cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[25:25]),
|
||||
.datab(wire_add_sub_cella_datab[25:25]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[25:25]));
|
||||
defparam
|
||||
add_sub_cella_25.cin_used = "true",
|
||||
add_sub_cella_25.lut_mask = "69b2",
|
||||
add_sub_cella_25.operation_mode = "arithmetic",
|
||||
add_sub_cella_25.sum_lutc_input = "cin",
|
||||
add_sub_cella_25.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_26
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_25cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_26cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[26:26]),
|
||||
.datab(wire_add_sub_cella_datab[26:26]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[26:26]));
|
||||
defparam
|
||||
add_sub_cella_26.cin_used = "true",
|
||||
add_sub_cella_26.lut_mask = "69b2",
|
||||
add_sub_cella_26.operation_mode = "arithmetic",
|
||||
add_sub_cella_26.sum_lutc_input = "cin",
|
||||
add_sub_cella_26.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_27
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_26cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_27cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[27:27]),
|
||||
.datab(wire_add_sub_cella_datab[27:27]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[27:27]));
|
||||
defparam
|
||||
add_sub_cella_27.cin_used = "true",
|
||||
add_sub_cella_27.lut_mask = "69b2",
|
||||
add_sub_cella_27.operation_mode = "arithmetic",
|
||||
add_sub_cella_27.sum_lutc_input = "cin",
|
||||
add_sub_cella_27.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_28
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_27cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_28cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[28:28]),
|
||||
.datab(wire_add_sub_cella_datab[28:28]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[28:28]));
|
||||
defparam
|
||||
add_sub_cella_28.cin_used = "true",
|
||||
add_sub_cella_28.lut_mask = "69b2",
|
||||
add_sub_cella_28.operation_mode = "arithmetic",
|
||||
add_sub_cella_28.sum_lutc_input = "cin",
|
||||
add_sub_cella_28.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_29
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_28cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_29cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[29:29]),
|
||||
.datab(wire_add_sub_cella_datab[29:29]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[29:29]));
|
||||
defparam
|
||||
add_sub_cella_29.cin_used = "true",
|
||||
add_sub_cella_29.lut_mask = "69b2",
|
||||
add_sub_cella_29.operation_mode = "arithmetic",
|
||||
add_sub_cella_29.sum_lutc_input = "cin",
|
||||
add_sub_cella_29.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_30
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_29cout[0:0]),
|
||||
.clk(clock),
|
||||
.cout(wire_add_sub_cella_30cout[0:0]),
|
||||
.dataa(wire_add_sub_cella_dataa[30:30]),
|
||||
.datab(wire_add_sub_cella_datab[30:30]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[30:30]));
|
||||
defparam
|
||||
add_sub_cella_30.cin_used = "true",
|
||||
add_sub_cella_30.lut_mask = "69b2",
|
||||
add_sub_cella_30.operation_mode = "arithmetic",
|
||||
add_sub_cella_30.sum_lutc_input = "cin",
|
||||
add_sub_cella_30.lpm_type = "stratix_lcell";
|
||||
stratix_lcell add_sub_cella_31
|
||||
(
|
||||
.aclr(aclr),
|
||||
.cin(wire_add_sub_cella_30cout[0:0]),
|
||||
.clk(clock),
|
||||
.dataa(wire_add_sub_cella_dataa[31:31]),
|
||||
.datab(wire_add_sub_cella_datab[31:31]),
|
||||
.ena(clken),
|
||||
.regout(wire_add_sub_cella_regout[31:31]));
|
||||
defparam
|
||||
add_sub_cella_31.cin_used = "true",
|
||||
add_sub_cella_31.lut_mask = "6969",
|
||||
add_sub_cella_31.operation_mode = "normal",
|
||||
add_sub_cella_31.sum_lutc_input = "cin",
|
||||
add_sub_cella_31.lpm_type = "stratix_lcell";
|
||||
assign
|
||||
wire_add_sub_cella_dataa = dataa,
|
||||
wire_add_sub_cella_datab = datab;
|
||||
assign
|
||||
result = wire_add_sub_cella_regout;
|
||||
endmodule //sub32_add_sub_cqa
|
||||
//VALID FILE
|
||||
|
||||
|
||||
module sub32 (
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
aclr,
|
||||
clken,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input clock;
|
||||
input aclr;
|
||||
input clken;
|
||||
output [31:0] result;
|
||||
|
||||
wire [31:0] sub_wire0;
|
||||
wire [31:0] result = sub_wire0[31:0];
|
||||
|
||||
sub32_add_sub_cqa sub32_add_sub_cqa_component (
|
||||
.dataa (dataa),
|
||||
.datab (datab),
|
||||
.clken (clken),
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.result (sub_wire0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: Function NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
|
||||
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
|
||||
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
|
||||
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
||||
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
//Copyright (C) 1991-2003 Altera Corporation
|
||||
//Any megafunction design, and related netlist (encrypted or decrypted),
|
||||
//support information, device programming or simulation file, and any other
|
||||
//associated documentation or information provided by Altera or a partner
|
||||
//under Altera's Megafunction Partnership Program may be used only
|
||||
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
//other use of such megafunction design, netlist, support information,
|
||||
//device programming or simulation file, or any other related documentation
|
||||
//or information is prohibited for any other purpose, including, but not
|
||||
//limited to modification, reverse engineering, de-compiling, or use with
|
||||
//any other silicon devices, unless such use is explicitly licensed under
|
||||
//a separate agreement with Altera or a megafunction partner. Title to the
|
||||
//intellectual property, including patents, copyrights, trademarks, trade
|
||||
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
||||
//support information, device programming or simulation file, or any other
|
||||
//related documentation or information provided by Altera or a megafunction
|
||||
//partner, remains with Altera, the megafunction partner, or their respective
|
||||
//licensors. No other licenses, including any licenses needed under any third
|
||||
//party's intellectual property, are provided herein.
|
||||
|
||||
module sub32 (
|
||||
dataa,
|
||||
datab,
|
||||
clock,
|
||||
aclr,
|
||||
clken,
|
||||
result)/* synthesis synthesis_clearbox = 1 */;
|
||||
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input clock;
|
||||
input aclr;
|
||||
input clken;
|
||||
output [31:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
sub32 sub32_inst (
|
||||
.dataa ( dataa_sig ),
|
||||
.datab ( datab_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.aclr ( aclr_sig ),
|
||||
.clken ( clken_sig ),
|
||||
.result ( result_sig )
|
||||
);
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
|
||||
// Model for tristate bus on altera
|
||||
// FIXME do we really need to use a megacell for this?
|
||||
|
||||
module bustri (data,
|
||||
enabledt,
|
||||
tridata);
|
||||
|
||||
input [15:0] data;
|
||||
input enabledt;
|
||||
inout [15:0] tridata;
|
||||
|
||||
assign tridata = enabledt ? data :16'bz;
|
||||
|
||||
endmodule // bustri
|
||||
|
||||
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
// Model of FIFO in Altera
|
||||
|
||||
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
parameter width = 16;
|
||||
parameter depth = 1024;
|
||||
parameter addr_bits = 10;
|
||||
|
||||
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
|
||||
|
||||
input [width-1:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [width-1:0] q;
|
||||
output rdfull;
|
||||
output rdempty;
|
||||
output reg [addr_bits-1:0] rdusedw;
|
||||
output wrfull;
|
||||
output wrempty;
|
||||
output reg [addr_bits-1:0] wrusedw;
|
||||
|
||||
reg [width-1:0] mem [0:depth-1];
|
||||
reg [addr_bits-1:0] rdptr;
|
||||
reg [addr_bits-1:0] wrptr;
|
||||
|
||||
`ifdef rd_req
|
||||
reg [width-1:0] q;
|
||||
`else
|
||||
wire [width-1:0] q;
|
||||
`endif
|
||||
|
||||
integer i;
|
||||
|
||||
always @( aclr)
|
||||
begin
|
||||
wrptr <= #1 0;
|
||||
rdptr <= #1 0;
|
||||
for(i=0;i<depth;i=i+1)
|
||||
mem[i] <= #1 0;
|
||||
end
|
||||
|
||||
always @(posedge wrclk)
|
||||
if(wrreq)
|
||||
begin
|
||||
wrptr <= #1 wrptr+1;
|
||||
mem[wrptr] <= #1 data;
|
||||
end
|
||||
|
||||
always @(posedge rdclk)
|
||||
if(rdreq)
|
||||
begin
|
||||
rdptr <= #1 rdptr+1;
|
||||
`ifdef rd_req
|
||||
q <= #1 mem[rdptr];
|
||||
`endif
|
||||
end
|
||||
|
||||
`ifdef rd_req
|
||||
`else
|
||||
assign q = mem[rdptr];
|
||||
`endif
|
||||
|
||||
// Fix these
|
||||
always @(posedge wrclk)
|
||||
wrusedw <= #1 wrptr - rdptr;
|
||||
|
||||
always @(posedge rdclk)
|
||||
rdusedw <= #1 wrptr - rdptr;
|
||||
|
||||
assign wrempty = (wrusedw == 0);
|
||||
assign wrfull = (wrusedw == depth-1);
|
||||
|
||||
assign rdempty = (rdusedw == 0);
|
||||
assign rdfull = (rdusedw == depth-1);
|
||||
|
||||
endmodule // fifo
|
||||
|
||||
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
// Model of FIFO in Altera
|
||||
|
||||
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
parameter width = 32;
|
||||
parameter depth = 1024;
|
||||
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
|
||||
|
||||
input [31:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [31:0] q;
|
||||
output rdfull;
|
||||
output rdempty;
|
||||
output [9:0] rdusedw;
|
||||
output wrfull;
|
||||
output wrempty;
|
||||
output [9:0] wrusedw;
|
||||
|
||||
reg [width-1:0] mem [0:depth-1];
|
||||
reg [7:0] rdptr;
|
||||
reg [7:0] wrptr;
|
||||
|
||||
`ifdef rd_req
|
||||
reg [width-1:0] q;
|
||||
`else
|
||||
wire [width-1:0] q;
|
||||
`endif
|
||||
|
||||
reg [9:0] rdusedw;
|
||||
reg [9:0] wrusedw;
|
||||
|
||||
integer i;
|
||||
|
||||
always @( aclr)
|
||||
begin
|
||||
wrptr <= #1 0;
|
||||
rdptr <= #1 0;
|
||||
for(i=0;i<depth;i=i+1)
|
||||
mem[i] <= #1 0;
|
||||
end
|
||||
|
||||
always @(posedge wrclk)
|
||||
if(wrreq)
|
||||
begin
|
||||
wrptr <= #1 wrptr+1;
|
||||
mem[wrptr] <= #1 data;
|
||||
end
|
||||
|
||||
always @(posedge rdclk)
|
||||
if(rdreq)
|
||||
begin
|
||||
rdptr <= #1 rdptr+1;
|
||||
`ifdef rd_req
|
||||
q <= #1 mem[rdptr];
|
||||
`endif
|
||||
end
|
||||
|
||||
`ifdef rd_req
|
||||
`else
|
||||
assign q = mem[rdptr];
|
||||
`endif
|
||||
|
||||
// Fix these
|
||||
always @(posedge wrclk)
|
||||
wrusedw <= #1 wrptr - rdptr;
|
||||
|
||||
always @(posedge rdclk)
|
||||
rdusedw <= #1 wrptr - rdptr;
|
||||
|
||||
assign wrempty = (wrusedw == 0);
|
||||
assign wrfull = (wrusedw == depth-1);
|
||||
|
||||
assign rdempty = (rdusedw == 0);
|
||||
assign rdfull = (rdusedw == depth-1);
|
||||
|
||||
endmodule // fifo_1c_1k
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
// Model of FIFO in Altera
|
||||
|
||||
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
parameter width = 32;
|
||||
parameter depth = 2048;
|
||||
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
|
||||
|
||||
input [31:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [31:0] q;
|
||||
output rdfull;
|
||||
output rdempty;
|
||||
output [10:0] rdusedw;
|
||||
output wrfull;
|
||||
output wrempty;
|
||||
output [10:0] wrusedw;
|
||||
|
||||
reg [width-1:0] mem [0:depth-1];
|
||||
reg [7:0] rdptr;
|
||||
reg [7:0] wrptr;
|
||||
|
||||
`ifdef rd_req
|
||||
reg [width-1:0] q;
|
||||
`else
|
||||
wire [width-1:0] q;
|
||||
`endif
|
||||
|
||||
reg [10:0] rdusedw;
|
||||
reg [10:0] wrusedw;
|
||||
|
||||
integer i;
|
||||
|
||||
always @( aclr)
|
||||
begin
|
||||
wrptr <= #1 0;
|
||||
rdptr <= #1 0;
|
||||
for(i=0;i<depth;i=i+1)
|
||||
mem[i] <= #1 0;
|
||||
end
|
||||
|
||||
always @(posedge wrclk)
|
||||
if(wrreq)
|
||||
begin
|
||||
wrptr <= #1 wrptr+1;
|
||||
mem[wrptr] <= #1 data;
|
||||
end
|
||||
|
||||
always @(posedge rdclk)
|
||||
if(rdreq)
|
||||
begin
|
||||
rdptr <= #1 rdptr+1;
|
||||
`ifdef rd_req
|
||||
q <= #1 mem[rdptr];
|
||||
`endif
|
||||
end
|
||||
|
||||
`ifdef rd_req
|
||||
`else
|
||||
assign q = mem[rdptr];
|
||||
`endif
|
||||
|
||||
// Fix these
|
||||
always @(posedge wrclk)
|
||||
wrusedw <= #1 wrptr - rdptr;
|
||||
|
||||
always @(posedge rdclk)
|
||||
rdusedw <= #1 wrptr - rdptr;
|
||||
|
||||
assign wrempty = (wrusedw == 0);
|
||||
assign wrfull = (wrusedw == depth-1);
|
||||
|
||||
assign rdempty = (rdusedw == 0);
|
||||
assign rdfull = (rdusedw == depth-1);
|
||||
|
||||
endmodule // fifo_1c_2k
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
// Model of FIFO in Altera
|
||||
|
||||
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
parameter width = 32;
|
||||
parameter depth = 4096;
|
||||
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
|
||||
|
||||
input [31:0] data;
|
||||
input wrreq;
|
||||
input rdreq;
|
||||
input rdclk;
|
||||
input wrclk;
|
||||
input aclr;
|
||||
output [31:0] q;
|
||||
output rdfull;
|
||||
output rdempty;
|
||||
output [7:0] rdusedw;
|
||||
output wrfull;
|
||||
output wrempty;
|
||||
output [7:0] wrusedw;
|
||||
|
||||
reg [width-1:0] mem [0:depth-1];
|
||||
reg [7:0] rdptr;
|
||||
reg [7:0] wrptr;
|
||||
|
||||
`ifdef rd_req
|
||||
reg [width-1:0] q;
|
||||
`else
|
||||
wire [width-1:0] q;
|
||||
`endif
|
||||
|
||||
reg [7:0] rdusedw;
|
||||
reg [7:0] wrusedw;
|
||||
|
||||
integer i;
|
||||
|
||||
always @( aclr)
|
||||
begin
|
||||
wrptr <= #1 0;
|
||||
rdptr <= #1 0;
|
||||
for(i=0;i<depth;i=i+1)
|
||||
mem[i] <= #1 0;
|
||||
end
|
||||
|
||||
always @(posedge wrclk)
|
||||
if(wrreq)
|
||||
begin
|
||||
wrptr <= #1 wrptr+1;
|
||||
mem[wrptr] <= #1 data;
|
||||
end
|
||||
|
||||
always @(posedge rdclk)
|
||||
if(rdreq)
|
||||
begin
|
||||
rdptr <= #1 rdptr+1;
|
||||
`ifdef rd_req
|
||||
q <= #1 mem[rdptr];
|
||||
`endif
|
||||
end
|
||||
|
||||
`ifdef rd_req
|
||||
`else
|
||||
assign q = mem[rdptr];
|
||||
`endif
|
||||
|
||||
// Fix these
|
||||
always @(posedge wrclk)
|
||||
wrusedw <= #1 wrptr - rdptr;
|
||||
|
||||
always @(posedge rdclk)
|
||||
rdusedw <= #1 wrptr - rdptr;
|
||||
|
||||
|
||||
endmodule // fifo_1c_4k
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
|
||||
|
||||
module fifo_1k
|
||||
( input [15:0] data,
|
||||
input wrreq,
|
||||
input rdreq,
|
||||
input rdclk,
|
||||
input wrclk,
|
||||
input aclr,
|
||||
output [15:0] q,
|
||||
output rdfull,
|
||||
output rdempty,
|
||||
output [9:0] rdusedw,
|
||||
output wrfull,
|
||||
output wrempty,
|
||||
output [9:0] wrusedw
|
||||
);
|
||||
|
||||
fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k
|
||||
( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
endmodule // fifo_1k
|
||||
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
|
||||
|
||||
module fifo_2k
|
||||
( input [15:0] data,
|
||||
input wrreq,
|
||||
input rdreq,
|
||||
input rdclk,
|
||||
input wrclk,
|
||||
input aclr,
|
||||
output [15:0] q,
|
||||
output rdfull,
|
||||
output rdempty,
|
||||
output [10:0] rdusedw,
|
||||
output wrfull,
|
||||
output wrempty,
|
||||
output [10:0] wrusedw
|
||||
);
|
||||
|
||||
fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k
|
||||
( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
endmodule // fifo_1k
|
||||
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
|
||||
|
||||
module fifo_4k
|
||||
( input [15:0] data,
|
||||
input wrreq,
|
||||
input rdreq,
|
||||
input rdclk,
|
||||
input wrclk,
|
||||
input aclr,
|
||||
output [15:0] q,
|
||||
output rdfull,
|
||||
output rdempty,
|
||||
output [11:0] rdusedw,
|
||||
output wrfull,
|
||||
output wrempty,
|
||||
output [11:0] wrusedw
|
||||
);
|
||||
|
||||
fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k
|
||||
( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
endmodule // fifo_1k
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
|
||||
|
||||
module fifo_4k_18
|
||||
(input [17:0] data,
|
||||
input wrreq,
|
||||
input wrclk,
|
||||
output wrfull,
|
||||
output wrempty,
|
||||
output [11:0] wrusedw,
|
||||
|
||||
output [17:0] q,
|
||||
input rdreq,
|
||||
input rdclk,
|
||||
output rdfull,
|
||||
output rdempty,
|
||||
output [11:0] rdusedw,
|
||||
|
||||
input aclr );
|
||||
|
||||
fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k
|
||||
( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
|
||||
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
||||
|
||||
endmodule // fifo_4k_18
|
||||
|
||||
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
// Very simple model for the PLL in the RX buffer
|
||||
|
||||
module pll (inclk0,c0);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
|
||||
assign c0 = #9 inclk0;
|
||||
|
||||
endmodule // pll
|
||||
|
||||
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
|
||||
// Model of Pipelined [ZBT] Synchronous SRAM
|
||||
|
||||
module ssram(clock,addr,data,wen,ce);
|
||||
parameter addrbits = 19;
|
||||
parameter depth = 524288;
|
||||
|
||||
input clock;
|
||||
input [addrbits-1:0] addr;
|
||||
inout [35:0] data;
|
||||
input wen;
|
||||
input ce;
|
||||
|
||||
reg [35:0] ram [0:depth-1];
|
||||
|
||||
reg read_d1,read_d2;
|
||||
reg write_d1,write_d2;
|
||||
reg [addrbits-1:0] addr_d1,addr_d2;
|
||||
|
||||
always @(posedge clock)
|
||||
begin
|
||||
read_d1 <= #1 ce & ~wen;
|
||||
write_d1 <= #1 ce & wen;
|
||||
addr_d1 <= #1 addr;
|
||||
read_d2 <= #1 read_d1;
|
||||
write_d2 <= #1 write_d1;
|
||||
addr_d2 <= #1 addr_d1;
|
||||
if(write_d2)
|
||||
ram[addr_d2] = data;
|
||||
end // always @ (posedge clock)
|
||||
|
||||
data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
|
||||
|
||||
always @(posedge clock)
|
||||
if(~ce & (write_d2 | write_d1 | wen))
|
||||
$display("$time ERROR: RAM CE not asserted during write cycle");
|
||||
|
||||
endmodule // ssram
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
/db
|
||||
/*.vcd
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
|
||||
|
||||
`include "../../firmware/include/fpga_regs_common.v"
|
||||
`include "../../firmware/include/fpga_regs_standard.v"
|
||||
|
||||
module adc_interface
|
||||
(input clock, input reset, input enable,
|
||||
input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
|
||||
input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b,
|
||||
output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3,
|
||||
output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q,
|
||||
output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q,
|
||||
output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q,
|
||||
output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q,
|
||||
output wire [3:0] rx_numchan);
|
||||
|
||||
// Buffer at input to chip
|
||||
reg [11:0] adc0,adc1,adc2,adc3;
|
||||
always @(posedge clock)
|
||||
begin
|
||||
adc0 <= #1 rx_a_a;
|
||||
adc1 <= #1 rx_b_a;
|
||||
adc2 <= #1 rx_a_b;
|
||||
adc3 <= #1 rx_b_b;
|
||||
end
|
||||
|
||||
// then scale and subtract dc offset
|
||||
wire [3:0] dco_en;
|
||||
wire [15:0] adc0_corr,adc1_corr,adc2_corr,adc3_corr;
|
||||
|
||||
setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
|
||||
.out(dco_en));
|
||||
|
||||
rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
|
||||
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
|
||||
rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3'b0}),.adc_out(adc1_corr),
|
||||
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
|
||||
rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3'b0}),.adc_out(adc2_corr),
|
||||
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
|
||||
rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3'b0}),.adc_out(adc3_corr),
|
||||
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
|
||||
|
||||
// Level sensing for AGC
|
||||
rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16]));
|
||||
rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16]));
|
||||
rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16]));
|
||||
rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16]));
|
||||
|
||||
// And mux to the appropriate outputs
|
||||
wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
|
||||
wire rx_realsignals;
|
||||
|
||||
setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
|
||||
.in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
|
||||
assign rx_numchan[0] = 1'b0;
|
||||
|
||||
always @(posedge clock)
|
||||
begin
|
||||
ddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr);
|
||||
ddc0_in_q <= #1 rx_realsignals ? 16'd0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr);
|
||||
ddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr);
|
||||
ddc1_in_q <= #1 rx_realsignals ? 16'd0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr);
|
||||
ddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr);
|
||||
ddc2_in_q <= #1 rx_realsignals ? 16'd0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr);
|
||||
ddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr);
|
||||
ddc3_in_q <= #1 rx_realsignals ? 16'd0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr);
|
||||
end
|
||||
|
||||
endmodule // adc_interface
|
||||
|
||||
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2007 Corgan Enterprises LLC
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
|
||||
input clk_i;
|
||||
input rst_i;
|
||||
input ena_i;
|
||||
input tx_empty_i;
|
||||
input [11:0] tx_delay_i;
|
||||
input [11:0] rx_delay_i;
|
||||
output atr_tx_o;
|
||||
|
||||
reg [3:0] state;
|
||||
reg [11:0] count;
|
||||
|
||||
`define ST_RX_DELAY 4'b0001
|
||||
`define ST_RX 4'b0010
|
||||
`define ST_TX_DELAY 4'b0100
|
||||
`define ST_TX 4'b1000
|
||||
|
||||
always @(posedge clk_i)
|
||||
if (rst_i | ~ena_i)
|
||||
begin
|
||||
state <= `ST_RX;
|
||||
count <= 12'b0;
|
||||
end
|
||||
else
|
||||
case (state)
|
||||
`ST_RX:
|
||||
if (!tx_empty_i)
|
||||
begin
|
||||
state <= `ST_TX_DELAY;
|
||||
count <= tx_delay_i;
|
||||
end
|
||||
|
||||
`ST_TX_DELAY:
|
||||
if (count == 0)
|
||||
state <= `ST_TX;
|
||||
else
|
||||
count <= count - 1;
|
||||
|
||||
`ST_TX:
|
||||
if (tx_empty_i)
|
||||
begin
|
||||
state <= `ST_RX_DELAY;
|
||||
count <= rx_delay_i;
|
||||
end
|
||||
|
||||
`ST_RX_DELAY:
|
||||
if (count == 0)
|
||||
state <= `ST_RX;
|
||||
else
|
||||
count <= count - 1;
|
||||
|
||||
default: // Error
|
||||
begin
|
||||
state <= `ST_RX;
|
||||
count <= 0;
|
||||
end
|
||||
endcase
|
||||
|
||||
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
|
||||
|
||||
endmodule // atr_delay
|
||||
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
// Bidirectional registers
|
||||
|
||||
module bidir_reg
|
||||
( inout wire [15:0] tristate,
|
||||
input wire [15:0] oe,
|
||||
input wire [15:0] reg_val );
|
||||
|
||||
// This would be much cleaner if all the tools
|
||||
// supported "for generate"........
|
||||
|
||||
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
|
||||
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
|
||||
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
|
||||
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
|
||||
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
|
||||
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
|
||||
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
|
||||
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
|
||||
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
|
||||
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
|
||||
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
|
||||
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
|
||||
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
|
||||
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
|
||||
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
|
||||
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
|
||||
|
||||
endmodule // bidir_reg
|
||||
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
// NOTE This only works for N=4, max decim rate of 128
|
||||
// NOTE signal "rate" is ONE LESS THAN the actual rate
|
||||
|
||||
module cic_dec_shifter(rate,signal_in,signal_out);
|
||||
parameter bw = 16;
|
||||
parameter maxbitgain = 28;
|
||||
|
||||
input [7:0] rate;
|
||||
input wire [bw+maxbitgain-1:0] signal_in;
|
||||
output reg [bw-1:0] signal_out;
|
||||
|
||||
function [4:0] bitgain;
|
||||
input [7:0] rate;
|
||||
case(rate)
|
||||
// Exact Cases -- N*log2(rate)
|
||||
8'd4 : bitgain = 8;
|
||||
8'd8 : bitgain = 12;
|
||||
8'd16 : bitgain = 16;
|
||||
8'd32 : bitgain = 20;
|
||||
8'd64 : bitgain = 24;
|
||||
8'd128 : bitgain = 28;
|
||||
|
||||
// Nearest without overflow -- ceil(N*log2(rate))
|
||||
8'd5 : bitgain = 10;
|
||||
8'd6 : bitgain = 11;
|
||||
8'd7 : bitgain = 12;
|
||||
8'd9 : bitgain = 13;
|
||||
8'd10,8'd11 : bitgain = 14;
|
||||
8'd12,8'd13 : bitgain = 15;
|
||||
8'd14,8'd15 : bitgain = 16;
|
||||
8'd17,8'd18,8'd19 : bitgain = 17;
|
||||
8'd20,8'd21,8'd22 : bitgain = 18;
|
||||
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
|
||||
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
|
||||
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
|
||||
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
|
||||
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
|
||||
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
|
||||
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
|
||||
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
|
||||
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
|
||||
default : bitgain = 28;
|
||||
endcase // case(rate)
|
||||
endfunction // bitgain
|
||||
|
||||
wire [4:0] shift = bitgain(rate+1);
|
||||
|
||||
// We should be able to do this, but can't ....
|
||||
// assign signal_out = signal_in[shift+bw-1:shift];
|
||||
|
||||
always @*
|
||||
case(shift)
|
||||
5'd8 : signal_out = signal_in[8+bw-1:8];
|
||||
5'd10 : signal_out = signal_in[10+bw-1:10];
|
||||
5'd11 : signal_out = signal_in[11+bw-1:11];
|
||||
5'd12 : signal_out = signal_in[12+bw-1:12];
|
||||
5'd13 : signal_out = signal_in[13+bw-1:13];
|
||||
5'd14 : signal_out = signal_in[14+bw-1:14];
|
||||
5'd15 : signal_out = signal_in[15+bw-1:15];
|
||||
5'd16 : signal_out = signal_in[16+bw-1:16];
|
||||
5'd17 : signal_out = signal_in[17+bw-1:17];
|
||||
5'd18 : signal_out = signal_in[18+bw-1:18];
|
||||
5'd19 : signal_out = signal_in[19+bw-1:19];
|
||||
5'd20 : signal_out = signal_in[20+bw-1:20];
|
||||
5'd21 : signal_out = signal_in[21+bw-1:21];
|
||||
5'd22 : signal_out = signal_in[22+bw-1:22];
|
||||
5'd23 : signal_out = signal_in[23+bw-1:23];
|
||||
5'd24 : signal_out = signal_in[24+bw-1:24];
|
||||
5'd25 : signal_out = signal_in[25+bw-1:25];
|
||||
5'd26 : signal_out = signal_in[26+bw-1:26];
|
||||
5'd27 : signal_out = signal_in[27+bw-1:27];
|
||||
5'd28 : signal_out = signal_in[28+bw-1:28];
|
||||
|
||||
default : signal_out = signal_in[28+bw-1:28];
|
||||
endcase // case(shift)
|
||||
|
||||
endmodule // cic_dec_shifter
|
||||
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
module cic_decim
|
||||
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
|
||||
parameter bw = 16;
|
||||
parameter N = 4;
|
||||
parameter log2_of_max_rate = 7;
|
||||
parameter maxbitgain = N * log2_of_max_rate;
|
||||
|
||||
input clock;
|
||||
input reset;
|
||||
input enable;
|
||||
input [7:0] rate;
|
||||
input strobe_in,strobe_out;
|
||||
input [bw-1:0] signal_in;
|
||||
output [bw-1:0] signal_out;
|
||||
reg [bw-1:0] signal_out;
|
||||
wire [bw-1:0] signal_out_unreg;
|
||||
|
||||
wire [bw+maxbitgain-1:0] signal_in_ext;
|
||||
reg [bw+maxbitgain-1:0] integrator [0:N-1];
|
||||
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
|
||||
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
|
||||
reg [bw+maxbitgain-1:0] sampler;
|
||||
|
||||
integer i;
|
||||
|
||||
sign_extend #(bw,bw+maxbitgain)
|
||||
ext_input (.in(signal_in),.out(signal_in_ext));
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset)
|
||||
for(i=0;i<N;i=i+1)
|
||||
integrator[i] <= #1 0;
|
||||
else if (enable && strobe_in)
|
||||
begin
|
||||
integrator[0] <= #1 integrator[0] + signal_in_ext;
|
||||
for(i=1;i<N;i=i+1)
|
||||
integrator[i] <= #1 integrator[i] + integrator[i-1];
|
||||
end
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset)
|
||||
begin
|
||||
sampler <= #1 0;
|
||||
for(i=0;i<N;i=i+1)
|
||||
begin
|
||||
pipeline[i] <= #1 0;
|
||||
differentiator[i] <= #1 0;
|
||||
end
|
||||
end
|
||||
else if (enable && strobe_out)
|
||||
begin
|
||||
sampler <= #1 integrator[N-1];
|
||||
differentiator[0] <= #1 sampler;
|
||||
pipeline[0] <= #1 sampler - differentiator[0];
|
||||
for(i=1;i<N;i=i+1)
|
||||
begin
|
||||
differentiator[i] <= #1 pipeline[i-1];
|
||||
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
|
||||
end
|
||||
end // if (enable && strobe_out)
|
||||
|
||||
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
|
||||
|
||||
cic_dec_shifter #(bw)
|
||||
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
|
||||
|
||||
always @(posedge clock)
|
||||
signal_out <= #1 signal_out_unreg;
|
||||
|
||||
endmodule // cic_decim
|
||||
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
// NOTE This only works for N=4, max interp rate of 128
|
||||
// NOTE signal "rate" is ONE LESS THAN the actual rate
|
||||
|
||||
module cic_int_shifter(rate,signal_in,signal_out);
|
||||
parameter bw = 16;
|
||||
parameter maxbitgain = 21;
|
||||
|
||||
input [7:0] rate;
|
||||
input wire [bw+maxbitgain-1:0] signal_in;
|
||||
output reg [bw-1:0] signal_out;
|
||||
|
||||
function [4:0] bitgain;
|
||||
input [7:0] rate;
|
||||
case(rate)
|
||||
// Exact Cases
|
||||
8'd4 : bitgain = 6;
|
||||
8'd8 : bitgain = 9;
|
||||
8'd16 : bitgain = 12;
|
||||
8'd32 : bitgain = 15;
|
||||
8'd64 : bitgain = 18;
|
||||
8'd128 : bitgain = 21;
|
||||
|
||||
// Nearest without overflow
|
||||
8'd5 : bitgain = 7;
|
||||
8'd6 : bitgain = 8;
|
||||
8'd7 : bitgain = 9;
|
||||
8'd9,8'd10 : bitgain = 10;
|
||||
8'd11,8'd12 : bitgain = 11;
|
||||
8'd13,8'd14,8'd15 : bitgain = 12;
|
||||
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
|
||||
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
|
||||
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
|
||||
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
|
||||
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
|
||||
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
|
||||
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
|
||||
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
|
||||
|
||||
default : bitgain = 21;
|
||||
endcase // case(rate)
|
||||
endfunction // bitgain
|
||||
|
||||
wire [4:0] shift = bitgain(rate+1);
|
||||
|
||||
// We should be able to do this, but can't ....
|
||||
// assign signal_out = signal_in[shift+bw-1:shift];
|
||||
|
||||
always @*
|
||||
case(shift)
|
||||
5'd6 : signal_out = signal_in[6+bw-1:6];
|
||||
5'd9 : signal_out = signal_in[9+bw-1:9];
|
||||
5'd12 : signal_out = signal_in[12+bw-1:12];
|
||||
5'd15 : signal_out = signal_in[15+bw-1:15];
|
||||
5'd18 : signal_out = signal_in[18+bw-1:18];
|
||||
5'd21 : signal_out = signal_in[21+bw-1:21];
|
||||
|
||||
5'd7 : signal_out = signal_in[7+bw-1:7];
|
||||
5'd8 : signal_out = signal_in[8+bw-1:8];
|
||||
5'd10 : signal_out = signal_in[10+bw-1:10];
|
||||
5'd11 : signal_out = signal_in[11+bw-1:11];
|
||||
5'd13 : signal_out = signal_in[13+bw-1:13];
|
||||
5'd14 : signal_out = signal_in[14+bw-1:14];
|
||||
5'd16 : signal_out = signal_in[16+bw-1:16];
|
||||
5'd17 : signal_out = signal_in[17+bw-1:17];
|
||||
5'd19 : signal_out = signal_in[19+bw-1:19];
|
||||
5'd20 : signal_out = signal_in[20+bw-1:20];
|
||||
|
||||
default : signal_out = signal_in[21+bw-1:21];
|
||||
endcase // case(shift)
|
||||
|
||||
endmodule // cic_int_shifter
|
||||
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
|
||||
parameter bw = 16;
|
||||
parameter N = 4;
|
||||
parameter log2_of_max_rate = 7;
|
||||
parameter maxbitgain = (N-1)*log2_of_max_rate;
|
||||
|
||||
input clock;
|
||||
input reset;
|
||||
input enable;
|
||||
input [7:0] rate;
|
||||
input strobe_in,strobe_out;
|
||||
input [bw-1:0] signal_in;
|
||||
wire [bw-1:0] signal_in;
|
||||
output [bw-1:0] signal_out;
|
||||
wire [bw-1:0] signal_out;
|
||||
|
||||
wire [bw+maxbitgain-1:0] signal_in_ext;
|
||||
reg [bw+maxbitgain-1:0] integrator [0:N-1];
|
||||
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
|
||||
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
|
||||
|
||||
integer i;
|
||||
|
||||
sign_extend #(bw,bw+maxbitgain)
|
||||
ext_input (.in(signal_in),.out(signal_in_ext));
|
||||
|
||||
wire clear_me = reset | ~enable;
|
||||
//FIXME Note that this section has pipe and diff reversed
|
||||
// It still works, but is confusing
|
||||
always @(posedge clock)
|
||||
if(clear_me)
|
||||
for(i=0;i<N;i=i+1)
|
||||
integrator[i] <= #1 0;
|
||||
else if (enable & strobe_out)
|
||||
begin
|
||||
if(strobe_in)
|
||||
integrator[0] <= #1 integrator[0] + pipeline[N-1];
|
||||
for(i=1;i<N;i=i+1)
|
||||
integrator[i] <= #1 integrator[i] + integrator[i-1];
|
||||
end
|
||||
|
||||
always @(posedge clock)
|
||||
if(clear_me)
|
||||
begin
|
||||
for(i=0;i<N;i=i+1)
|
||||
begin
|
||||
differentiator[i] <= #1 0;
|
||||
pipeline[i] <= #1 0;
|
||||
end
|
||||
end
|
||||
else if (enable && strobe_in)
|
||||
begin
|
||||
differentiator[0] <= #1 signal_in_ext;
|
||||
pipeline[0] <= #1 signal_in_ext - differentiator[0];
|
||||
for(i=1;i<N;i=i+1)
|
||||
begin
|
||||
differentiator[i] <= #1 pipeline[i-1];
|
||||
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
|
||||
end
|
||||
end
|
||||
|
||||
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
|
||||
|
||||
cic_int_shifter #(bw)
|
||||
cic_int_shifter(rate,signal_out_unnorm,signal_out);
|
||||
|
||||
endmodule // cic_interp
|
||||
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
|
||||
reg [7:0] counter;
|
||||
|
||||
// FIXME maybe should use PLL or switch to double edge version
|
||||
|
||||
always @(posedge in_clk or posedge reset)
|
||||
if(reset)
|
||||
counter <= #1 8'd0;
|
||||
else if(counter == 0)
|
||||
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
|
||||
else
|
||||
counter <= #1 counter-8'd1;
|
||||
|
||||
always @(posedge in_clk or posedge reset)
|
||||
if(reset)
|
||||
out_clk <= #1 1'b0;
|
||||
else if(counter == 0)
|
||||
out_clk <= #1 ~out_clk;
|
||||
|
||||
endmodule // clk_divider
|
||||
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
|
||||
parameter bitwidth = 16;
|
||||
parameter zwidth = 16;
|
||||
|
||||
input clock;
|
||||
input reset;
|
||||
input enable;
|
||||
input [bitwidth-1:0] xi, yi;
|
||||
output [bitwidth-1:0] xo, yo;
|
||||
input [zwidth-1:0] zi;
|
||||
output [zwidth-1:0] zo;
|
||||
|
||||
reg [bitwidth+1:0] x0,y0;
|
||||
reg [zwidth-2:0] z0;
|
||||
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
|
||||
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
|
||||
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
|
||||
|
||||
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
|
||||
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
|
||||
|
||||
// Compute consts. Would be easier if vlog had atan...
|
||||
// see gen_cordic_consts.py
|
||||
|
||||
`define c00 16'd8192
|
||||
`define c01 16'd4836
|
||||
`define c02 16'd2555
|
||||
`define c03 16'd1297
|
||||
`define c04 16'd651
|
||||
`define c05 16'd326
|
||||
`define c06 16'd163
|
||||
`define c07 16'd81
|
||||
`define c08 16'd41
|
||||
`define c09 16'd20
|
||||
`define c10 16'd10
|
||||
`define c11 16'd5
|
||||
`define c12 16'd3
|
||||
`define c13 16'd1
|
||||
`define c14 16'd1
|
||||
`define c15 16'd0
|
||||
`define c16 16'd0
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset)
|
||||
begin
|
||||
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
|
||||
end
|
||||
else if(enable)
|
||||
begin
|
||||
z0 <= #1 zi[zwidth-2:0];
|
||||
case (zi[zwidth-1:zwidth-2])
|
||||
2'b00, 2'b11 :
|
||||
begin
|
||||
x0 <= #1 xi_ext;
|
||||
y0 <= #1 yi_ext;
|
||||
end
|
||||
2'b01, 2'b10 :
|
||||
begin
|
||||
x0 <= #1 -xi_ext;
|
||||
y0 <= #1 -yi_ext;
|
||||
end
|
||||
endcase // case(zi[zwidth-1:zwidth-2])
|
||||
end // else: !if(reset)
|
||||
|
||||
// FIXME need to handle variable number of stages
|
||||
// FIXME should be able to narrow zwidth but quartus makes it bigger...
|
||||
// This would be easier if arrays worked better in vlog...
|
||||
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
|
||||
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
|
||||
|
||||
assign xo = x12[bitwidth:1];
|
||||
assign yo = y12[bitwidth:1];
|
||||
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
|
||||
//assign yo = y12[bitwidth+1:2];
|
||||
assign zo = z12;
|
||||
|
||||
endmodule // cordic
|
||||
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
|
||||
parameter bitwidth = 16;
|
||||
parameter zwidth = 16;
|
||||
parameter shift = 1;
|
||||
|
||||
input clock;
|
||||
input reset;
|
||||
input enable;
|
||||
input [bitwidth-1:0] xi,yi;
|
||||
input [zwidth-1:0] zi;
|
||||
input [zwidth-1:0] constant;
|
||||
output [bitwidth-1:0] xo,yo;
|
||||
output [zwidth-1:0] zo;
|
||||
|
||||
wire z_is_pos = ~zi[zwidth-1];
|
||||
|
||||
reg [bitwidth-1:0] xo,yo;
|
||||
reg [zwidth-1:0] zo;
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset)
|
||||
begin
|
||||
xo <= #1 0;
|
||||
yo <= #1 0;
|
||||
zo <= #1 0;
|
||||
end
|
||||
else if(enable)
|
||||
begin
|
||||
xo <= #1 z_is_pos ?
|
||||
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
|
||||
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
|
||||
yo <= #1 z_is_pos ?
|
||||
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
|
||||
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
|
||||
zo <= #1 z_is_pos ?
|
||||
zi - constant :
|
||||
zi + constant;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
|
||||
// DDC block
|
||||
|
||||
module ddc(input clock,
|
||||
input reset,
|
||||
input enable,
|
||||
input [3:0] rate1,
|
||||
input [3:0] rate2,
|
||||
output strobe,
|
||||
input [31:0] freq,
|
||||
input [15:0] i_in,
|
||||
input [15:0] q_in,
|
||||
output [15:0] i_out,
|
||||
output [15:0] q_out
|
||||
);
|
||||
parameter bw = 16;
|
||||
parameter zw = 16;
|
||||
|
||||
wire [15:0] i_cordic_out, q_cordic_out;
|
||||
wire [31:0] phase;
|
||||
|
||||
wire strobe1, strobe2;
|
||||
reg [3:0] strobe_ctr1,strobe_ctr2;
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset | ~enable)
|
||||
strobe_ctr2 <= #1 4'd0;
|
||||
else if(strobe2)
|
||||
strobe_ctr2 <= #1 4'd0;
|
||||
else
|
||||
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset | ~enable)
|
||||
strobe_ctr1 <= #1 4'd0;
|
||||
else if(strobe1)
|
||||
strobe_ctr1 <= #1 4'd0;
|
||||
else if(strobe2)
|
||||
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
|
||||
|
||||
|
||||
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
|
||||
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
|
||||
|
||||
assign strobe = strobe1;
|
||||
|
||||
function [2:0] log_ceil;
|
||||
input [3:0] val;
|
||||
|
||||
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
|
||||
endfunction
|
||||
|
||||
wire [2:0] shift1 = log_ceil(rate1);
|
||||
wire [2:0] shift2 = log_ceil(rate2);
|
||||
|
||||
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
|
||||
cordic(.clock(clock), .reset(reset), .enable(enable),
|
||||
.xi(i_in), .yi(q_in), .zi(phase[31:32-zw]),
|
||||
.xo(i_cordic_out), .yo(q_cordic_out), .zo() );
|
||||
|
||||
cic_decim_2stage #(.bw(bw),.N(4))
|
||||
decim_i(.clock(clock),.reset(reset),.enable(enable),
|
||||
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
|
||||
.signal_in(i_cordic_out),.signal_out(i_out));
|
||||
|
||||
cic_decim_2stage #(.bw(bw),.N(4))
|
||||
decim_q(.clock(clock),.reset(reset),.enable(enable),
|
||||
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
|
||||
.signal_in(q_cordic_out),.signal_out(q_out));
|
||||
|
||||
phase_acc #(.resolution(32))
|
||||
nco (.clk(clock),.reset(reset),.enable(enable),
|
||||
.freq(freq),.phase(phase));
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
|
||||
|
||||
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
|
||||
parameter depth = 4;
|
||||
parameter width = 16;
|
||||
parameter size = 16;
|
||||
|
||||
input wclk;
|
||||
input [width-1:0] wdata;
|
||||
input [depth-1:0] waddr;
|
||||
input wen;
|
||||
|
||||
input rclk;
|
||||
output reg [width-1:0] rdata;
|
||||
input [depth-1:0] raddr;
|
||||
|
||||
reg [width-1:0] ram [0:size-1];
|
||||
|
||||
always @(posedge wclk)
|
||||
if(wen)
|
||||
ram[waddr] <= #1 wdata;
|
||||
|
||||
always @(posedge rclk)
|
||||
rdata <= #1 ram[raddr];
|
||||
|
||||
endmodule // dpram
|
||||
|
|
@ -1,95 +0,0 @@
|
|||
// -*- verilog -*-
|
||||
//
|
||||
// USRP - Universal Software Radio Peripheral
|
||||
//
|
||||
// Copyright (C) 2003 Matt Ettus
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
// DUC block
|
||||
|
||||
module duc(input clock,
|
||||
input reset,
|
||||
input enable,
|
||||
input [3:0] rate1,
|
||||
input [3:0] rate2,
|
||||
output strobe,
|
||||
input [31:0] freq,
|
||||
input [15:0] i_in,
|
||||
input [15:0] q_in,
|
||||
output [15:0] i_out,
|
||||
output [15:0] q_out
|
||||
);
|
||||
parameter bw = 16;
|
||||
parameter zw = 16;
|
||||
|
||||
wire [15:0] i_interp_out, q_interp_out;
|
||||
wire [31:0] phase;
|
||||
|
||||
wire strobe1, strobe2;
|
||||
reg [3:0] strobe_ctr1,strobe_ctr2;
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset | ~enable)
|
||||
strobe_ctr2 <= #1 4'd0;
|
||||
else if(strobe2)
|
||||
strobe_ctr2 <= #1 4'd0;
|
||||
else
|
||||
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
|
||||
|
||||
always @(posedge clock)
|
||||
if(reset | ~enable)
|
||||
strobe_ctr1 <= #1 4'd0;
|
||||
else if(strobe1)
|
||||
strobe_ctr1 <= #1 4'd0;
|
||||
else if(strobe2)
|
||||
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
|
||||
|
||||
|
||||
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
|
||||
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
|
||||
|
||||
assign strobe = strobe1;
|
||||
|
||||
function [2:0] log_ceil;
|
||||
input [3:0] val;
|
||||
|
||||
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
|
||||
endfunction
|
||||
|
||||
wire [2:0] shift1 = log_ceil(rate1);
|
||||
wire [2:0] shift2 = log_ceil(rate2);
|
||||
|
||||
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
|
||||
cordic(.clock(clock), .reset(reset), .enable(enable),
|
||||
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
|
||||
.xo(i_out), .yo(q_out), .zo() );
|
||||
|
||||
cic_interp_2stage #(.bw(bw),.N(4))
|
||||
interp_i(.clock(clock),.reset(reset),.enable(enable),
|
||||
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
|
||||
.signal_in(i_in),.signal_out(i_interp_out));
|
||||
|
||||
cic_interp_2stage #(.bw(bw),.N(4))
|
||||
interp_q(.clock(clock),.reset(reset),.enable(enable),
|
||||
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
|
||||
.signal_in(q_in),.signal_out(q_interp_out));
|
||||
|
||||
phase_acc #(.resolution(32))
|
||||
nco (.clk(clock),.reset(reset),.enable(enable),
|
||||
.freq(freq),.phase(phase));
|
||||
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue