diff --git a/firmware/include/fpga_regs_standard.h b/firmware/include/fpga_regs_standard.h
index 2f119fe..6ae8b6c 100644
--- a/firmware/include/fpga_regs_standard.h
+++ b/firmware/include/fpga_regs_standard.h
@@ -185,7 +185,7 @@
 // FIXME register numbers 50 to 63 are available
 
 // ------------------------------------------------------------------------
-// Registers 64 to 79 are reserved for user custom FPGA builds.
+// Registers 64 to 95 are reserved for user custom FPGA builds.
 // The standard USRP software will not touch these.
 
 #define FR_USER_0	64
@@ -204,6 +204,22 @@
 #define FR_USER_13	77
 #define FR_USER_14	78
 #define FR_USER_15	79
+#define FR_USER_16	80
+#define FR_USER_17	81
+#define FR_USER_18	82
+#define FR_USER_19	83
+#define FR_USER_20	84
+#define FR_USER_21	85
+#define FR_USER_22	86
+#define FR_USER_23	87
+#define FR_USER_24	88
+#define FR_USER_25	89
+#define FR_USER_26	90
+#define FR_USER_27	91
+#define FR_USER_28	92
+#define FR_USER_29	93
+#define FR_USER_30	94
+#define FR_USER_31	95
 
 //Registers needed for multi usrp master/slave configuration
 //
diff --git a/firmware/include/fpga_regs_standard.v b/firmware/include/fpga_regs_standard.v
index cc67be2..b88bcdd 100644
--- a/firmware/include/fpga_regs_standard.v
+++ b/firmware/include/fpga_regs_standard.v
@@ -157,7 +157,7 @@
 // FIXME register numbers 50 to 63 are available
 
 // ------------------------------------------------------------------------
-// Registers 64 to 79 are reserved for user custom FPGA builds.
+// Registers 64 to 95 are reserved for user custom FPGA builds.
 // The standard USRP software will not touch these.
 
 `define FR_USER_0                 7'd64
@@ -176,6 +176,22 @@
 `define FR_USER_13                7'd77
 `define FR_USER_14                7'd78
 `define FR_USER_15                7'd79
+`define FR_USER_16                7'd80
+`define FR_USER_17                7'd81
+`define FR_USER_18                7'd82
+`define FR_USER_19                7'd83
+`define FR_USER_20                7'd84
+`define FR_USER_21                7'd85
+`define FR_USER_22                7'd86
+`define FR_USER_23                7'd87
+`define FR_USER_24                7'd88
+`define FR_USER_25                7'd89
+`define FR_USER_26                7'd90
+`define FR_USER_27                7'd91
+`define FR_USER_28                7'd92
+`define FR_USER_29                7'd93
+`define FR_USER_30                7'd94
+`define FR_USER_31                7'd95
 
 //Registers needed for multi usrp master/slave configuration
 //
diff --git a/fpga/rbf/rev2/std_2rxhb_2tx.rbf b/fpga/rbf/rev2/std_2rxhb_2tx.rbf
index 340a683..71c3013 100755
Binary files a/fpga/rbf/rev2/std_2rxhb_2tx.rbf and b/fpga/rbf/rev2/std_2rxhb_2tx.rbf differ
diff --git a/fpga/rbf/rev4/std_2rxhb_2tx.rbf b/fpga/rbf/rev4/std_2rxhb_2tx.rbf
index 340a683..71c3013 100755
Binary files a/fpga/rbf/rev4/std_2rxhb_2tx.rbf and b/fpga/rbf/rev4/std_2rxhb_2tx.rbf differ
diff --git a/fpga/sdr_lib/cordic.v b/fpga/sdr_lib/cordic.v
index fee241f..ea41194 100755
--- a/fpga/sdr_lib/cordic.v
+++ b/fpga/sdr_lib/cordic.v
@@ -66,7 +66,7 @@ module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
        begin
 	  x0   <= #1 0; y0   <= #1 0;  z0   <= #1 0;
        end
-     else// if(enable)
+     else if(enable)
        begin
 	  z0 <= #1 zi[zwidth-2:0];
 	  case (zi[zwidth-1:zwidth-2])
diff --git a/fpga/sdr_lib/cordic_stage.v b/fpga/sdr_lib/cordic_stage.v
index 0106da5..d44998b 100755
--- a/fpga/sdr_lib/cordic_stage.v
+++ b/fpga/sdr_lib/cordic_stage.v
@@ -45,7 +45,7 @@ module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
 	  yo <= #1 0;
 	  zo <= #1 0;
        end
-     else //if(enable)
+     else if(enable)
        begin
 	  xo <= #1 z_is_pos ?   
 		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :