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Fix compilation with newer sdcc 

Since recent system upgrade which pulled in sdcc 4.3.0, build fails with
following error:
/git/libusrp/firmware/include/fx2regs.h:324: syntax error: token -> '+' ; column 26

It seems newer sdcc doesn't like having sums directly in there. Using
parenthesis around the expression fixes the problem.

Related: OS#6157
Change-Id: Iccc0b1ffe95971957f16008c3e3b873d065ba0ea
This commit is contained in:
Pau Espin 2023-08-29 12:48:03 +02:00
parent d1d39c65a3
commit 573075bfed
2 changed files with 75 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

140
firmware/include/fx2regs.h
View File

@ -321,7 +321,7 @@ __sfr __at 0x84 DPL1;
__sfr __at 0x85 DPH1;
__sfr __at 0x86 DPS;
/* DPS */
__sbit __at 0x86+0 SEL;
__sbit __at (0x86+0) SEL;
__sfr __at 0x87 PCON; /* PCON */
//__sbit IDLE = 0x87+0;
//__sbit STOP = 0x87+1;
@ -330,14 +330,14 @@ __sfr __at 0x87 PCON; /* PCON */
//__sbit SMOD0 = 0x87+7;
__sfr __at 0x88 TCON;
/* TCON */
__sbit __at 0x88+0 IT0;
__sbit __at 0x88+1 IE0;
__sbit __at 0x88+2 IT1;
__sbit __at 0x88+3 IE1;
__sbit __at 0x88+4 TR0;
__sbit __at 0x88+5 TF0;
__sbit __at 0x88+6 TR1;
__sbit __at 0x88+7 TF1;
__sbit __at (0x88+0) IT0;
__sbit __at (0x88+1) IE0;
__sbit __at (0x88+2) IT1;
__sbit __at (0x88+3) IE1;
__sbit __at (0x88+4) TR0;
__sbit __at (0x88+5) TF0;
__sbit __at (0x88+6) TR1;
__sbit __at (0x88+7) TF1;
__sfr __at 0x89 TMOD;
/* TMOD */
//__sbit M00 = 0x89+0;
@ -373,14 +373,14 @@ __sfr __at 0x91 EXIF; // EXIF Bit Values differ from Reg320
__sfr __at 0x92 MPAGE;
__sfr __at 0x98 SCON0;
/* SCON0 */
__sbit __at 0x98+0 RI;
__sbit __at 0x98+1 TI;
__sbit __at 0x98+2 RB8;
__sbit __at 0x98+3 TB8;
__sbit __at 0x98+4 REN;
__sbit __at 0x98+5 SM2;
__sbit __at 0x98+6 SM1;
__sbit __at 0x98+7 SM0;
__sbit __at (0x98+0) RI;
__sbit __at (0x98+1) TI;
__sbit __at (0x98+2) RB8;
__sbit __at (0x98+3) TB8;
__sbit __at (0x98+4) REN;
__sbit __at (0x98+5) SM2;
__sbit __at (0x98+6) SM1;
__sbit __at (0x98+7) SM0;
__sfr __at 0x99 SBUF0;
__sfr __at 0x9A APTR1H;
@ -398,14 +398,14 @@ __sfr __at 0xA2 INT4CLR;
__sfr __at 0xA8 IE;
/* IE */
__sbit __at 0xA8+0 EX0;
__sbit __at 0xA8+1 ET0;
__sbit __at 0xA8+2 EX1;
__sbit __at 0xA8+3 ET1;
__sbit __at 0xA8+4 ES0;
__sbit __at 0xA8+5 ET2;
__sbit __at 0xA8+6 ES1;
__sbit __at 0xA8+7 EA;
__sbit __at (0xA8+0) EX0;
__sbit __at (0xA8+1) ET0;
__sbit __at (0xA8+2) EX1;
__sbit __at (0xA8+3) ET1;
__sbit __at (0xA8+4) ES0;
__sbit __at (0xA8+5) ET2;
__sbit __at (0xA8+6) ES1;
__sbit __at (0xA8+7) EA;
__sfr __at 0xAA EP2468STAT;
/* EP2468STAT */
@ -436,13 +436,13 @@ __sfr __at 0xB6 OEE;
__sfr __at 0xB8 IP;
/* IP */
__sbit __at 0xB8+0 PX0;
__sbit __at 0xB8+1 PT0;
__sbit __at 0xB8+2 PX1;
__sbit __at 0xB8+3 PT1;
__sbit __at 0xB8+4 PS0;
__sbit __at 0xB8+5 PT2;
__sbit __at 0xB8+6 PS1;
__sbit __at (0xB8+0) PX0;
__sbit __at (0xB8+1) PT0;
__sbit __at (0xB8+2) PX1;
__sbit __at (0xB8+3) PT1;
__sbit __at (0xB8+4) PS0;
__sbit __at (0xB8+5) PT2;
__sbit __at (0xB8+6) PS1;
__sfr __at 0xBA EP01STAT;
__sfr __at 0xBB GPIFTRIG;
@ -453,61 +453,61 @@ __sfr __at 0xBF GPIFSGLDATLNOX;
__sfr __at 0xC0 SCON1;
/* SCON1 */
__sbit __at 0xC0+0 RI1;
__sbit __at 0xC0+1 TI1;
__sbit __at 0xC0+2 RB81;
__sbit __at 0xC0+3 TB81;
__sbit __at 0xC0+4 REN1;
__sbit __at 0xC0+5 SM21;
__sbit __at 0xC0+6 SM11;
__sbit __at 0xC0+7 SM01;
__sbit __at (0xC0+0) RI1;
__sbit __at (0xC0+1) TI1;
__sbit __at (0xC0+2) RB81;
__sbit __at (0xC0+3) TB81;
__sbit __at (0xC0+4) REN1;
__sbit __at (0xC0+5) SM21;
__sbit __at (0xC0+6) SM11;
__sbit __at (0xC0+7) SM01;
__sfr __at 0xC1 SBUF1;
__sfr __at 0xC8 T2CON;
/* T2CON */
__sbit __at 0xC8+0 CP_RL2;
__sbit __at 0xC8+1 C_T2;
__sbit __at 0xC8+2 TR2;
__sbit __at 0xC8+3 EXEN2;
__sbit __at 0xC8+4 TCLK;
__sbit __at 0xC8+5 RCLK;
__sbit __at 0xC8+6 EXF2;
__sbit __at 0xC8+7 TF2;
__sbit __at (0xC8+0) CP_RL2;
__sbit __at (0xC8+1) C_T2;
__sbit __at (0xC8+2) TR2;
__sbit __at (0xC8+3) EXEN2;
__sbit __at (0xC8+4) TCLK;
__sbit __at (0xC8+5) RCLK;
__sbit __at (0xC8+6) EXF2;
__sbit __at (0xC8+7) TF2;
__sfr __at 0xCA RCAP2L;
__sfr __at 0xCB RCAP2H;
__sfr __at 0xCC TL2;
__sfr __at 0xCD TH2;
__sfr __at 0xD0 PSW;
/* PSW */
__sbit __at 0xD0+0 P;
__sbit __at 0xD0+1 FL;
__sbit __at 0xD0+2 OV;
__sbit __at 0xD0+3 RS0;
__sbit __at 0xD0+4 RS1;
__sbit __at 0xD0+5 F0;
__sbit __at 0xD0+6 AC;
__sbit __at 0xD0+7 CY;
__sbit __at (0xD0+0) P;
__sbit __at (0xD0+1) FL;
__sbit __at (0xD0+2) OV;
__sbit __at (0xD0+3) RS0;
__sbit __at (0xD0+4) RS1;
__sbit __at (0xD0+5) F0;
__sbit __at (0xD0+6) AC;
__sbit __at (0xD0+7) CY;
__sfr __at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
/* EICON */
__sbit __at 0xD8+3 INT6;
__sbit __at 0xD8+4 RESI;
__sbit __at 0xD8+5 ERESI;
__sbit __at 0xD8+7 SMOD1;
__sbit __at (0xD8+3) INT6;
__sbit __at (0xD8+4) RESI;
__sbit __at (0xD8+5) ERESI;
__sbit __at (0xD8+7) SMOD1;
__sfr __at 0xE0 ACC;
__sfr __at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
__sbit __at 0xE8+0 EIUSB;
__sbit __at 0xE8+1 EI2C;
__sbit __at 0xE8+2 EIEX4;
__sbit __at 0xE8+3 EIEX5;
__sbit __at 0xE8+4 EIEX6;
__sbit __at (0xE8+0) EIUSB;
__sbit __at (0xE8+1) EI2C;
__sbit __at (0xE8+2) EIEX4;
__sbit __at (0xE8+3) EIEX5;
__sbit __at (0xE8+4) EIEX6;
__sfr __at 0xF0 B;
__sfr __at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
__sbit __at 0xF8+0 PUSB;
__sbit __at 0xF8+1 PI2C;
__sbit __at 0xF8+2 EIPX4;
__sbit __at 0xF8+3 EIPX5;
__sbit __at 0xF8+4 EIPX6;
__sbit __at (0xF8+0) PUSB;
__sbit __at (0xF8+1) PI2C;
__sbit __at (0xF8+2) EIPX4;
__sbit __at (0xF8+3) EIPX5;
__sbit __at (0xF8+4) EIPX6;
/*-----------------------------------------------------------------------------
Bit Masks

10
firmware/src/usrp2/usrp_rev2_regs.h
View File

@ -47,9 +47,9 @@
#define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow)
__sbit __at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A
__sbit __at 0x80+1 bitS_OUT; // out from FX2 point of view
__sbit __at 0x80+2 bitS_IN; // in from FX2 point of view
__sbit __at (0x80+0) bitS_CLK; // 0x80 is the bit address of PORT A
__sbit __at (0x80+1) bitS_OUT; // out from FX2 point of view
__sbit __at (0x80+2) bitS_IN; // in from FX2 point of view
/* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */
@ -85,8 +85,8 @@ __sbit __at 0x80+2 bitS_IN; // in from FX2 point of view
#define bmPC_LED0 bmBIT6 // active low
#define bmPC_LED1 bmBIT7 // active low
__sbit __at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C
__sbit __at 0xA0+3 bitALTERA_DCLK;
__sbit __at (0xA0+1) bitALTERA_DATA0; // 0xA0 is the bit address of PORT C
__sbit __at (0xA0+3) bitALTERA_DCLK;
#define bmALTERA_BITS (bmALTERA_DATA0 \