Andreas Bogk c8747f28d8 Piotr's pipelined implementation.		2009-01-24 17:06:16 +01:00
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Piotr	Piotr's pipelined implementation.	2009-01-24 17:06:16 +01:00
a5.v	Verilog implementation of A5.	2009-01-15 17:33:58 +01:00