367 lines
11 KiB
C
Executable File
367 lines
11 KiB
C
Executable File
/***************************************************************************
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* sdla_bri.h Sangoma ISDN-BRI definitions (for Cologne XHFC-2SU chip).
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*
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* Author(s): David Rokhvarg <davidr@sangoma.com>
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*
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* Copyright: (c) 1984 - 2007 Sangoma Technologies Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* ============================================================================
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* February 14, 2007 David Rokhvarg
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* v1.0 Initial version.
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*
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* February 26, 2008 David Rokhvarg
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* v1.1 Imrovements in SU State transition code.
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* Implemented T3 and T4 timers.
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*
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******************************************************************************
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*/
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#ifndef __SDLA_BRI_H
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# define __SDLA_BRI_H
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#if defined(__LINUX__)
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# include <linux/xhfc24succ.h>
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#else
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# include <xhfc24succ.h>
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#endif
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/*******************************************************************************
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** DEFINES and MACROS
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*******************************************************************************/
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#define IS_BRI_CARD(card) IS_BRI_FEMEDIA(&(card)->fe)
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#define WAN_BRI_START_CHANNEL 1
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#define MAX_BRI_REMORAS 4
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#define MAX_BRI_MODULES_PER_REMORA 3
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/*
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Maximum of 4 remoras, 3 modules on each - maximum 12 modules.
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On each module there is 1 dual-port ISDN BRI chip.
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On each line there are 2 B-channels and 1 D-channel.
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*/
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#define MAX_BRI_MODULES 12
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#define MAX_BRI_CHANNELS 2 /* Number of channels per device */
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#define MAX_BRI_LINES (MAX_BRI_MODULES*MAX_BRI_CHANNELS)
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/*
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The maximum number of BRI timeslots is 32.
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This is needed for the d-chan, which is always at the otherwise unused timeslot 31.
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But AFT hardware is actually using only 24 timeslots - only for the b-chans.
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*/
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#define MAX_TIMESLOTS 32
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#define BRI_DCHAN_LOGIC_CHAN 31
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#define BRI_DCHAN_ACTIVE_CFG_CHAN 2
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#define MAX_BRI_TIMESLOTS 3 /* this is the number of b-chans (2) and the d-chan on one BRI line */
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#define MAX_TENT_CHANNELS MAX_BRI_MODULES
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#define MOD_TYPE_NONE 0 /* corresponds to module which is not installed */
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#define MOD_TYPE_NT 1
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#define MOD_TYPE_TE 2
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#define MOD_TYPE_TEST 3
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#define WP_BRI_DECODE_MOD_TYPE(type) \
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(type == MOD_TYPE_NT) ? "NT" : \
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(type == MOD_TYPE_TE) ? "TE" : "Unknown"
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/* SPI interface */
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#define MOD_CHAIN_DISABLED 0
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#define MOD_CHAIN_ENABLED 1
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#define SPI_INTERFACE_REG 0x54
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#define SPI_MAX_RETRY_COUNT 10
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#define MOD_SPI_RESET 0x40000000
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#define MOD_SPI_BUSY 0x80000000
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#define MOD_SPI_V3_STAT 0x08000000 /* bit 27 used as START in version 1-2-3 */
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#define MOD_SPI_START 0x08000000
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#define BRI_FE_MAGIC 0x150D
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#define WAN_BRI_OPERMODE_LEN 20
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#if !defined(__WINDOWS__)
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/* Front-End UDP command */
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#define WAN_FE_TONES (WAN_FE_UDP_CMD_START + 0)
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#define WAN_FE_RING (WAN_FE_UDP_CMD_START + 1)
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#define WAN_FE_REGDUMP (WAN_FE_UDP_CMD_START + 2)
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#define WAN_FE_STATS (WAN_FE_UDP_CMD_START + 3)
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#define WAN_BRI_SET_ECHOTUNE _IOW (ZT_CODE, 63, struct wan_bri_echo_coefs)
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#endif
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/******************************************************************************
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** XHFC definitions
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*******************************************************************************/
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/* max. number of S/U ports per XHFC-2SU controller */
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#define BRI_MAX_PORTS_PER_CHIP 2
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#define PORT_0 0
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#define PORT_1 1
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/* flags in _u16 port mode */
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#define PORT_UNUSED 0x0000
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#define PORT_MODE_NT 0x0001
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#define PORT_MODE_TE 0x0002
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#define PORT_MODE_S0 0x0004
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#define PORT_MODE_UP 0x0008
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#define PORT_MODE_EXCH_POL 0x0010
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#define PORT_MODE_LOOP 0x0020
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#define NT_TIMER 0x8000
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/* NT / TE defines */
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#define NT_T1_COUNT 25 /* number of 4ms interrupts for G2 timeout */
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#define CLK_DLY_TE 0x0e /* CLKDEL in TE mode */
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#define CLK_DLY_NT 0x6c /* CLKDEL in NT mode */
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#define STA_ACTIVATE 0x60 /* start activation in A_SU_WR_STA */
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#define STA_DEACTIVATE 0x40 /* start deactivation in A_SU_WR_STA */
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#define LIF_MODE_NT 0x04 /* Line Interface NT mode */
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#define XHFC_TIMER_T3 8000 /* 8s activation timer T3 */
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#define XHFC_TIMER_T4 500 /* 500ms deactivation timer T4 */
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/* xhfc Layer1 physical commands */
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#define HFC_L1_ACTIVATE_TE 0x01
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#define HFC_L1_FORCE_DEACTIVATE_TE 0x02
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#define HFC_L1_ACTIVATE_NT 0x03
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#define HFC_L1_DEACTIVATE_NT 0x04
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#define HFC_L1_TESTLOOP_B1 0x05
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#define HFC_L1_TESTLOOP_B2 0x06
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/* xhfc Layer1 Flags (stored in bri_xhfc_port_t->l1_flags) */
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#define HFC_L1_ACTIVATING 1
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#define HFC_L1_ACTIVATED 2
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#define HFC_L1_DEACTTIMER 4
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#define HFC_L1_ACTTIMER 8
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/* Layer1 timer Flags (stored in bri_xhfc_port_t->timer_flags) */
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#define T3_TIMER_ACTIVE 1
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#define T4_TIMER_ACTIVE 2
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#define FIFO_MASK_TX 0x55555555
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#define FIFO_MASK_RX 0xAAAAAAAA
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#ifndef MAX_DFRAME_LEN_L1
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#define MAX_DFRAME_LEN_L1 300
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#endif
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#define USE_F0_COUNTER 1 /* akkumulate F0 counter diff every irq */
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#define TRANSP_PACKET_SIZE 0 /* minium tranparent packet size for transmittion to upper layer */
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typedef struct sdla_bri_cfg_ {
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int not_used;
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int opermode;
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char opermode_name[WAN_BRI_OPERMODE_LEN];
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/* int tdmv_law;*/ /* WAN_TDMV_ALAW or WAN_TDMV_MULAW */
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char clock_mode;
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} sdla_bri_cfg_t;
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#if defined(WAN_KERNEL)
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#if !defined(WAN_DEBUG_FE)
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/* no debugging info compiled */
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/* NT/TE */
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# define WRITE_BRI_REG(mod_no,reg,val) \
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fe->write_fe_reg( fe->card, \
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(int)mod_no, \
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fe->bri_param.mod[mod_no].type, \
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fe->bri_param.mod[mod_no].chain, \
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(int)reg, (int)val)
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# define READ_BRI_REG(mod_no,reg) \
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fe->read_fe_reg( fe->card, \
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(int)mod_no, \
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fe->bri_param.mod[mod_no].type, \
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fe->bri_param.mod[mod_no].chain, \
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(int)reg)
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#else
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#warning "WAN_DEBUG_FE - Debugging Defined"
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/* NT/TE */
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# define WRITE_BRI_REG(mod_no,reg,val) \
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fe->write_fe_reg( fe->card, \
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(int)mod_no, \
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fe->bri_param.mod[mod_no].type, \
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fe->bri_param.mod[mod_no].chain, \
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(int)reg, (int)val,__FILE__,(int)__LINE__)
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# define READ_BRI_REG(mod_no,reg) \
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fe->read_fe_reg( fe->card, \
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(int)mod_no, \
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fe->bri_param.mod[mod_no].type, \
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fe->bri_param.mod[mod_no].chain, \
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(int)reg,__FILE__,(int)__LINE__)
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#endif/* #if !defined(WAN_DEBUG_FE) */
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#define __READ_BRI_REG(mod_no,reg) \
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fe->__read_fe_reg( fe->card, \
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(int)mod_no, \
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fe->bri_param.mod[mod_no].type, \
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fe->bri_param.mod[mod_no].chain, \
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(int)reg)
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/***************************************************************/
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/* port struct for each S/U port */
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typedef struct {
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u_int8_t idx; /* port idx in hw->port[idx] */
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void *hw; /* back pointer to 'wp_bri_module_t' */
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u_int16_t mode; /* NT/TE / ST/U */
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u_int32_t l1_flags;
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u_int32_t timer_flags;
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int drx_indx;
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int dtx_indx, bytes2transmit;
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u_int8_t drxbuf[MAX_DFRAME_LEN_L1];
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u_int8_t dtxbuf[MAX_DFRAME_LEN_L1];
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/* layer1 ISDN timer */
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wan_timer_t t3_timer;
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wan_timer_t t4_timer;
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/* chip registers */
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reg_a_su_rd_sta su_state;
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reg_a_su_ctrl0 su_ctrl0;
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reg_a_su_ctrl1 su_ctrl1;
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reg_a_su_ctrl2 su_ctrl2;
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reg_a_st_ctrl3 st_ctrl3;
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/* DavidR */
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reg_a_sl_cfg sl_cfg;/* for data direction programming on pins STIO1 and STIO2 */
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u_int32_t clock_routing_state, clock_routing_counter;
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u_int32_t l1_state;/* BRI L1 current state of the line */
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int nt_timer;
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} bri_xhfc_port_t;
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/*******************************************************************************
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** TYPEDEF STRUCTURE
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*******************************************************************************/
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typedef struct {
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unsigned int mod_no;
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/* Both ports of a module will always be in the
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SAME mode - TE or NT. */
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int type;
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int chain;
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unsigned long events;
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#if 0
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#if defined(__WINDOWS__)
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wan_event_ctrl_t current_control_event;
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wan_event_ctrl_t *current_control_event_ptr;
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#else
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WAN_LIST_HEAD(, wan_event_ctrl_) event_head;
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#endif
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#endif
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/* TDM Voice applications */
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int sig;
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/**********************************/
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int num_ports; /* number of S and U interfaces */
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int max_fifo; /* always 4 fifos per port */
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u_int8_t max_z; /* fifo depth -1 */
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bri_xhfc_port_t port[BRI_MAX_PORTS_PER_CHIP]; /* 2 ports - one for each Line intercace */
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u_int32_t irq_cnt; /* count irqs */
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u_int32_t f0_cnt; /* last F0 counter value */
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u_int32_t f0_akku; /* akkumulated f0 counter deltas */
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/* chip registers */
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reg_r_pcm_md0 pcm_md0;
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reg_r_pcm_md1 pcm_md1;
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/**********************************/
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void *fe; /* pointer back to 'sdla_fe_t' */
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} wp_bri_module_t;
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typedef struct {
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/* u_int16_t type; */
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unsigned int mod_no; /* A500 - ISDN BRI Remora */
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unsigned char ec_dtmf_port; /* EC DTMF: SOUT or ROUT */
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unsigned long ts_map;
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u_int8_t tone;
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} sdla_bri_event_t;
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typedef struct sdla_bri_param {
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int not_used;
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/* each module has 2 lines, */
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wp_bri_module_t mod[MAX_BRI_LINES];
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/*
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Maximum of 4 remoras, 3 modules on each - maximum 12 modules.
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On each module there is 1 dual-port ISDN BRI chip.
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On each line there are 2 B-channels and 1 D-channel.
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It means we have 48 timeslots (B-channels only!), and 32 bits are not enough.
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First 0-23 timeslots will be mapped on 'module_map[0]' and 24-47 will be mapped
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on 'module_map[1]'.
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*/
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u_int32_t module_map[2]; /* Map of available module */
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u_int16_t max_fe_channels; /* Number of available modules */
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u_int8_t critical;
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/*
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Flag indicating if this logical 'card' (sdla_t) which represents a BRI line,
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is the 'clock reference port' for the physical A500 card.
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Only ONE 'card' may have this flag set to WANOPT_YES, all others must be
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WANOPT_NO.
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TE mode: if 'is_clock_master' is set to WANOPT_YES, clock recovered from
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the line will be routed to ALL other BRI modules on the card.
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*/
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u_int8_t is_clock_master;
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} sdla_bri_param_t;
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/*******************************************************************************
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DEFINES AND MACROS
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*******************************************************************************/
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/* AFT register - Intel x86 definition. */
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typedef struct bri_reg{
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u_int32_t data:8; /* lsb */
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u_int32_t contrl:8;
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u_int32_t reserv1:8;
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u_int32_t mod_addr:2; /* 00, 01, 10 - adresses modules,
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code 11 - address of status register per-remora.
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*/
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u_int32_t remora_addr:4; /* Select Remora. Maximum is 4 (from 0 to 3) for BRI */
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u_int32_t reset:1;
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u_int32_t start:1;/* msb */
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}bri_reg_t;
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#define READ_BIT (1 << 7)
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#define ADDR_BIT (1 << 6)
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/*******************************************************************************
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** FUNCTION PROTOTYPES
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*******************************************************************************/
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extern int wp_bri_iface_init(void*);
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#endif/* WAN_KERNEL */
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/***************************************************************/
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#endif /* __SDLA_BRI_H */
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