129 lines
5.6 KiB
C
129 lines
5.6 KiB
C
/*****************************************************************************
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* sdlapci.h WANPIPE(tm) Multiprotocol WAN Link Driver.
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* Definitions for the SDLA PCI adapter.
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*
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* Author: Gideon Hack <ghack@sangoma.com>
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*
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* Copyright: (c) 1999-2000 Sangoma Technologies Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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* ============================================================================
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* Jun 02, 1999 Gideon Hack Initial version.
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*****************************************************************************/
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#ifndef _SDLAPCI_H
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#define _SDLAPCI_H
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/****** Defines *************************************************************/
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/* Definitions for identifying and finding S514 PCI adapters */
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#define V3_VENDOR_ID 0x11B0 /* V3 vendor ID number */
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#define V3_DEVICE_ID 0x0002 /* V3 device ID number */
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#define SANGOMA_SUBSYS_VENDOR 0x4753 /* ID for Sangoma */
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#define PCI_DEV_SLOT_MASK 0x1F /* mask for slot numbering */
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#define PCI_IRQ_NOT_ALLOCATED 0xFF /* interrupt line for no IRQ */
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/* Definition for identifying and finding XILINX PCI adapters */
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#define SANGOMA_PCI_VENDOR 0x1923 /* Old value -> 0x11B0 */
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#define SANGOMA_PCI_VENDOR_OLD 0x10EE /* Old value -> 0x11B0 */
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#define SANGOMA_PCI_DEVICE 0x0300 /* Old value -> 0x0200 */
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#define SANGOMA_PCI_4_DEVICE 0x0400 /* */
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#define A101_1TE1_SUBSYS_VENDOR 0xA010 /* A101 with T1/E1 1 line */
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#define A101_2TE1_SUBSYS_VENDOR 0xA011 /* A101 with T1/E1 2 lines */
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#define A104_4TE1_SUBSYS_VENDOR 0xA013 /* A104 with T1/E1 4 lines */
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#define A300_UTE3_SUBSYS_VENDOR 0xA020 /* A300 with T3/E3 (unchannelized) */
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#define A305_CT3_SUBSYS_VENDOR 0xA030 /* A305 with T3 (channelized) */
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#define A104_1TE1_SHARK_SUBSYS_VENDOR 0xA111 /* A101-SHARK T1/E1 1 lines */
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#define A104_2TE1_SHARK_SUBSYS_VENDOR 0xA112 /* A102-SHARK T1/E1 2 lines */
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#define A104_4TE1_SHARK_SUBSYS_VENDOR 0xA113 /* A104-SHARK T1/E1 4 lines */
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#define A104_8TE1_SHARK_SUBSYS_VENDOR 0xA114 /* A108-SHARK T1/E1 8 lines */
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#define A300_UTE3_SHARK_SUBSYS_VENDOR 0xA115 /* A300-SHARK with T3/E3 (unchannelized) */
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#define A305_CTE3_SHARK_SUBSYS_VENDOR 0xA116 /* A305-SHARK with T3 (channelized) */
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#define A200_REMORA_SHARK_SUBSYS_VENDOR 0xA200 /* AFT-REMORA SHARK analog board */
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#define AFT_CORE_ID_MASK 0x00FF
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#define AFT_CORE_REV_MASK 0xFF00
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#define AFT_HDLC_CORE_ID 0x00 /* HDLC core */
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#define AFT_ATM_CORE_ID 0x01 /* ATM core */
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#define AFT_SS7_CORE_ID 0x02 /* SS7 core */
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#define AFT_CHIP_UNKNOWN 0x0000
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#define AFT_CHIP_OLD_X300 0x0300
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#define AFT_CHIP_OLD_X400 0x0400
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#define AFT_CHIP_X300 0x0030
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#define AFT_CHIP_X400 0x0040
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#define AFT_CHIP_X1000 0x0100
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#define AFT_PCI_MEM_SIZE 0x2FF
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#define XILINX_PCI_LATENCY 0x0000FF00
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#define AFT4_PCI_MEM_SIZE 0xFFFF
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#define XILINX_PCI_CMD_REG 0x04
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#define XILINX_PCI_LATENCY_REG 0x0C
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/* Local PCI register offsets */
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#define PCI_VENDOR_ID_WORD 0x00 /* vendor ID */
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#define PCI_DEVICE_ID_WORD 0x02 /* device ID */
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#define PCI_REVISION_ID_BYTE 0x08 /* revision ID */
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#define PCI_SUBCLASS_ID_BYTE 0x0a /* subclass ID byte */
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#define PCI_IO_BASE_DWORD 0x10 /* IO base */
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#define PCI_MEM_BASE0_DWORD 0x14 /* memory base - apperture 0 */
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#define PCI_MEM_BASE1_DWORD 0x18 /* memory base - apperture 1 */
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#define PCI_SUBSYS_VENDOR_WORD 0x2C /* subsystem vendor ID */
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#define PCI_SUBSYS_ID_WORD 0x2E /* subsystem ID */
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#define PCI_INT_LINE_BYTE 0x3C /* interrupt line */
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#define PCI_INT_PIN_BYTE 0x3D /* interrupt pin */
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#define PCI_MAP0_DWORD 0x40 /* PCI to local bus address 0 */
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#define PCI_MAP1_DWORD 0x44 /* PCI to local bus address 1 */
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#define PCI_INT_STATUS 0x48 /* interrupt status */
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#define PCI_INT_CONFIG 0x4C /* interrupt configuration */
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/* Local PCI register usage */
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#define PCI_MEMORY_ENABLE 0x00000003 /* enable PCI memory */
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#define PCI_CPU_A_MEM_DISABLE 0x00000002 /* disable CPU A memory */
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#define PCI_CPU_B_MEM_DISABLE 0x00100002 /* disable CPU B memory */
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#define PCI_ENABLE_IRQ_CPU_A 0x005A0004 /* enable IRQ for CPU A */
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#define PCI_ENABLE_IRQ_CPU_B 0x005A0008 /* enable IRQ for CPU B */
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#define PCI_ENABLE_IRQ_DMA0 0x01000000 /* enable IRQ for DMA 0 */
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#define PCI_ENABLE_IRQ_DMA1 0x02000000 /* enable IRQ for DMA 1 */
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#define PCI_DISABLE_IRQ_CPU_A 0x00000004 /* disable IRQ for CPU A */
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#define PCI_DISABLE_IRQ_CPU_B 0x00000008 /* disable IRQ for CPU B */
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#define PCI_DISABLE_IRQ_DMA0 0x01000000 /* disable IRQ for DMA 0 */
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#define PCI_DISABLE_IRQ_DMA1 0x02000000 /* disable IRQ for DMA 1 */
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/* Setting for the Interrupt Status register */
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#define IRQ_DMA0 0x01000000 /* IRQ for DMA0 */
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#define IRQ_DMA1 0x02000000 /* IRQ for DMA1 */
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#define IRQ_LOCAL_CPU_A 0x00000004 /* IRQ for CPU A */
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#define IRQ_LOCAL_CPU_B 0x00000008 /* IRQ for CPU B */
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#define IRQ_CPU_A 0x04 /* IRQ for CPU A */
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#define IRQ_CPU_B 0x08 /* IRQ for CPU B */
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/* The maximum size of the S514 memory */
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#define MAX_SIZEOF_S514_MEMORY (256 * 1024)
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/* S514 control register offsets within the memory address space */
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#define S514_CTRL_REG_BYTE 0x80000
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/* S514 adapter control bytes */
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#define S514_CPU_HALT 0x00
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#define S514_CPU_START 0x01
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/* The maximum number of S514 adapters supported */
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#define MAX_S514_CARDS 20
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/* ADSL Hardware Defines */
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#define GSI_PCI_MEMORY_SIZE (8 * (4 * 2 * 1024))
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#define PCI_VENDOR_ID_GSI 0x14BC
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#define PCI_DEVICE_ID_GSI_PULSAR 0xD002
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#define PCI_DEVICE_ID_GSI_ADSL PCI_DEVICE_ID_GSI_PULSAR
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#endif /* _SDLAPCI_H */
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