674 lines
17 KiB
C
674 lines
17 KiB
C
/*
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* Copyright (c) 2001
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* Alex Feldman <al.feldman@sangoma.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Alex Feldman.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Alex Feldman AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Alex Feldman OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: sdla_te1_ds.h,v 1.9 2007/01/04 20:16:01 sangoma Exp $
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*/
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/*****************************************************************************
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* sdla_te1_ds.h Sangoma TE1 configuration definitions (Dallas).
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*
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* Author: Alex Feldman
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*
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* ============================================================================
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* Aprl 30, 2001 Alex Feldman Initial version.
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****************************************************************************
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*/
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#ifndef __SDLA_TE1_DS_H
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# define __SDLA_TE1_DS_H
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/******************************************************************************
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DEFINES AND MACROS
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******************************************************************************/
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/* Global Register Definitions */
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#define REG_GTCR1 0xF0
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#define REG_GFCR 0xF1
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#define BIT_GFCR_TCBCS 0x02
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#define BIT_GFCR_RCBCS 0x01
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#define REG_GTCR2 0xF2
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#define REG_GTCCR 0xF3
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#define REG_GLSRR 0xF5
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#define REG_GFSRR 0xF6
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#define REG_IDR 0xF8
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#define DEVICE_ID_DS26528 0x0B
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#define DEVICE_ID_DS26524 0x0C
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#define DEVICE_ID_DS26522 0x0D
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#define DEVICE_ID_DS26521 0x0E
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#define DEVICE_ID_SHIFT 3
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#define DEVICE_ID_MASK 0x1F
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#define DEVICE_ID_DS(dev_id) ((dev_id) >> DEVICE_ID_SHIFT) & DEVICE_ID_MASK
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#define DECODE_CHIPID(chip_id) \
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(chip_id == DEVICE_ID_DS26528) ? "DS26528" : \
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(chip_id == DEVICE_ID_DS26524) ? "DS26524" : \
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(chip_id == DEVICE_ID_DS26522) ? "DS26522" : \
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(chip_id == DEVICE_ID_DS26521) ? "DS26521" : "Unknown"
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#define REG_GFISR 0xF9
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#define REG_GBISR 0xFA
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#define REG_GLISR 0xFB
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#define REG_GFIMR 0xFC
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#define REG_GBIMR 0xFD
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#define REG_GLIMR 0xFE
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/* RX Framer Register Definitions */
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#define REG_RSIGC 0x13
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#define BIT_RSIGC_CASMS 0x10
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#define REG_RS1 0x40
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#define BIT_RS_A 0x08
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#define BIT_RS_B 0x04
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#define BIT_RS_C 0x02
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#define BIT_RS_D 0x01
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#define REG_RS2 0x41
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#define REG_RS3 0x42
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#define REG_RS4 0x43
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#define REG_RS5 0x44
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#define REG_RS6 0x45
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#define REG_RS7 0x46
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#define REG_RS8 0x47
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#define REG_RS9 0x48
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#define REG_RS10 0x49
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#define REG_RS11 0x4A
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#define REG_RS12 0x4B
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#define REG_RS13 0x4C
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#define REG_RS14 0x4D
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#define REG_RS15 0x4E
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#define REG_RS16 0x4F
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#define REG_LCVCR1 0x50
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#define REG_LCVCR2 0x51
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#define REG_PCVCR1 0x52
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#define REG_PCVCR2 0x53
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#define REG_FOSCR1 0x54
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#define REG_FOSCR2 0x55
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#define REG_E1EBCR1 0x56
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#define REG_E1EBCR2 0x57
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#define REG_RMMR 0x80
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#define BIT_RMMR_FRM_EN 0x80
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#define BIT_RMMR_INIT_DONE 0x40
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#define BIT_RMMR_SFTRST 0x02
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#define BIT_RMMR_T1E1 0x01
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#define REG_RCR1 0x81
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#define BIT_RCR1_T1_SYNCT 0x80
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#define BIT_RCR1_T1_RB8ZS 0x40
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#define BIT_RCR1_T1_RFM 0x20
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#define BIT_RCR1_T1_ARC 0x10
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#define BIT_RCR1_T1_SYNCC 0x08
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#define BIT_RCR1_T1_RJC 0x04
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#define BIT_RCR1_T1_SYNCE 0x02
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#define BIT_RCR1_T1_RESYNC 0x01
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#define BIT_RCR1_E1_RHDB3 0x40
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#define BIT_RCR1_E1_RSIGM 0x20
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#define BIT_RCR1_E1_RG802 0x10
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#define BIT_RCR1_E1_RCRC4 0x08
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#define BIT_RCR1_E1_FRC 0x04
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#define BIT_RCR1_E1_SYNCE 0x02
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#define BIT_RCR1_E1_RESYNC 0x01
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#define REG_RCR3 0x83
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#define BIT_RCR3_IDF 0x80
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#define BIT_RCR3_RSERC 0x20
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#define BIT_RCR3_PLB 0x02
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#define BIT_RCR3_FLB 0x01
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#define REG_RIOCR 0x84
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#define BIT_RIOCR_RCLKINV 0x80
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#define BIT_RIOCR_RSYNCINV 0x40
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#define BIT_RIOCR_H100EN 0x20
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#define BIT_RIOCR_RSCLKM 0x10
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#define BIT_RIOCR_RSMS 0x08
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#define BIT_RIOCR_RSIO 0x04
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#define BIT_RIOCR_RSMS2 0x02
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#define BIT_RIOCR_RSMS1 0x01
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#define REG_RESCR 0x85
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#define BIT_RESCR_RGCLKEN 0x40
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#define BIT_RESCR_RESE 0x01
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#define REG_ERCNT 0x86
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#define BIT_ERCNT_1SECS 0x80
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#define BIT_ERCNT_MCUS 0x40
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#define BIT_ERCNT_MECU 0x20
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#define BIT_ERCNT_ECUS 0x10
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#define BIT_ERCNT_EAMS 0x08
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#define BIT_ERCNT_FSBE 0x04
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#define BIT_ERCNT_MOSCR 0x02
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#define BIT_ERCNT_LCVCRF 0x01
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#define REG_RLS1 0x90
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#define BIT_RLS1_RRAIC 0x80
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#define BIT_RLS1_RAISC 0x40
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#define BIT_RLS1_RLOSC 0x20
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#define BIT_RLS1_RLOFC 0x10
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#define BIT_RLS1_RRAID 0x08
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#define BIT_RLS1_RAISD 0x04
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#define BIT_RLS1_RLOSD 0x02
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#define BIT_RLS1_RLOFD 0x01
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#define REG_RLS2 0x91
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#define BIT_RLS2_T1_RPDV 0x80
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#define BIT_RLS2_T1_COFA 0x20
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#define BIT_RLS2_T1_8ZD 0x10
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#define BIT_RLS2_T1_16ZD 0x08
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#define BIT_RLS2_T1_SEFE 0x04
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#define BIT_RLS2_T1_B8ZS 0x02
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#define BIT_RLS2_T1_FBE 0x01
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#define BIT_RLS2_E1_CRCRC 0x40
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#define BIT_RLS2_E1_CASRC 0x20
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#define BIT_RLS2_E1_FASRC 0x10
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#define BIT_RLS2_E1_RSA1 0x08
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#define BIT_RLS2_E1_RSA0 0x04
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#define BIT_RLS2_E1_RCMF 0x02
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#define BIT_RLS2_E1_RAF 0x01
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#define REG_RLS3 0x92
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#define BIT_RLS3_T1_LORCC 0x80
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#define BIT_RLS3_T1_LSPC 0x40
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#define BIT_RLS3_T1_LDNC 0x20
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#define BIT_RLS3_T1_LUPC 0x10
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#define BIT_RLS3_T1_LORCD 0x08
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#define BIT_RLS3_T1_LSPD 0x04
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#define BIT_RLS3_T1_LDND 0x02
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#define BIT_RLS3_T1_LUPD 0x01
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#define BIT_RLS3_E1_LORCC 0x80
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#define BIT_RLS3_E1_V52LNKC 0x20
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#define BIT_RLS3_E1_RDMAC 0x10
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#define BIT_RLS3_E1_LORCD 0x08
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#define BIT_RLS3_E1_V52LNKD 0x02
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#define BIT_RLS3_E1_RDMAD 0x01
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#define REG_RLS4 0x93
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#define BIT_RLS4_RESF 0x80
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#define BIT_RLS4_RESEM 0x40
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#define BIT_RLS4_RSLIP 0x20
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#define BIT_RLS4_RSCOS 0x08
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#define BIT_RLS4_1SEC 0x04
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#define BIT_RLS4_TIMER 0x02
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#define BIT_RLS4_RMF 0x01
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#define REG_RLS5 0x94
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#define BIT_RLS5_ROVR 0x20
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#define BIT_RLS5_RHOBT 0x10
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#define BIT_RLS5_RPE 0x08
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#define BIT_RLS5_RPS 0x03
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#define BIT_RLS5_RHWMS 0x02
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#define BIT_RLS5_RNES 0x01
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#define REG_RLS6 0x95
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#define REG_RLS7 0x96
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#define BIT_RLS7_RRAI_CI 0x20
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#define BIT_RLS7_RAIS_CI 0x10
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#define BIT_RLS7_RSLC96 0x08
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#define BIT_RLS7_RFDLF 0x04
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#define BIT_RLS7_BC 0x02
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#define BIT_RLS7_BD 0x01
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#define REG_RSS1 0x98
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#define BIT_RSS1_CH1 0x80
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#define BIT_RSS1_CH2 0x40
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#define BIT_RSS1_CH3 0x20
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#define BIT_RSS1_CH4 0x10
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#define BIT_RSS1_CH5 0x08
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#define BIT_RSS1_CH6 0x04
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#define BIT_RSS1_CH7 0x02
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#define BIT_RSS1_CH8 0x01
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#define REG_RSS2 0x99
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#define BIT_RSS2_CH9 0x80
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#define BIT_RSS2_CH10 0x40
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#define BIT_RSS2_CH11 0x20
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#define BIT_RSS2_CH12 0x10
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#define BIT_RSS2_CH13 0x08
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#define BIT_RSS2_CH14 0x04
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#define BIT_RSS2_CH15 0x02
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#define BIT_RSS2_CH16 0x01
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#define REG_RSS3 0x9A
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#define BIT_RSS3_CH17 0x80
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#define BIT_RSS3_CH18 0x40
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#define BIT_RSS3_CH19 0x20
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#define BIT_RSS3_CH20 0x10
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#define BIT_RSS3_CH21 0x08
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#define BIT_RSS3_CH22 0x04
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#define BIT_RSS3_CH23 0x02
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#define BIT_RSS3_CH24 0x01
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#define REG_RSS4 0x9B
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#define BIT_RSS4_CH25 0x80
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#define BIT_RSS4_CH26 0x40
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#define BIT_RSS4_CH27 0x20
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#define BIT_RSS4_CH28 0x10
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#define BIT_RSS4_CH29 0x08
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#define BIT_RSS4_CH30 0x04
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#define BIT_RSS4_CH31 0x02
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#define BIT_RSS4_CH32 0x01
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#define REG_RIIR 0x9F
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#define BIT_RIIR_RLS7 0x40
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#define BIT_RIIR_RLS6 0x20
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#define BIT_RIIR_RLS5 0x10
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#define BIT_RIIR_RLS4 0x08
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#define BIT_RIIR_RLS3 0x04
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#define BIT_RIIR_RLS2 0x02
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#define BIT_RIIR_RLS1 0x01
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#define REG_RIM1 0xA0
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#define BIT_RIM1_RRAIC 0x80
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#define BIT_RIM1_RAISC 0x40
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#define BIT_RIM1_RLOSC 0x20
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#define BIT_RIM1_RLOFC 0x10
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#define BIT_RIM1_RRAID 0x08
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#define BIT_RIM1_RAISD 0x04
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#define BIT_RIM1_RLOSD 0x02
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#define BIT_RIM1_RLOFD 0x01
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#define REG_RIM2 0xA1
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#define BIT_RIM2_E1_RSA1 0x08
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#define BIT_RIM2_E1_RSA0 0x04
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#define BIT_RIM2_E1_RCMF 0x02
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#define BIT_RIM2_E1_RAF 0x01
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#define REG_RIM3 0xA2
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#define BIT_RIM3_T1_LORCC 0x80
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#define BIT_RIM3_T1_LSPC 0x40
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#define BIT_RIM3_T1_LDNC 0x20
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#define BIT_RIM3_T1_LUPC 0x10
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#define BIT_RIM3_T1_LORCD 0x08
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#define BIT_RIM3_T1_LSPD 0x04
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#define BIT_RIM3_T1_LDND 0x02
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#define BIT_RIM3_T1_LUPD 0x01
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#define BIT_RIM3_E1_LORCC 0x80
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#define BIT_RIM3_E1_V52LNKC 0x20
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#define BIT_RIM3_E1_RDMAC 0x10
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#define BIT_RIM3_E1_LORCD 0x08
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#define BIT_RIM3_E1_V52LNKD 0x02
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#define BIT_RIM3_E1_RDMAD 0x01
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#define REG_RIM4 0xA3
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#define BIT_RIM4_RESF 0x80
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#define BIT_RIM4_RESEM 0x40
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#define BIT_RIM4_RSLIP 0x20
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#define BIT_RIM4_RSCOS 0x08
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#define BIT_RIM4_1SEC 0x04
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#define BIT_RIM4_TIMER 0x02
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#define BIT_RIM4_RMF 0x01
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#define REG_RIM5 0xA4
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#define BIT_RIM5_ROVR 0x20
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#define BIT_RIM5_RHOBT 0x10
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#define BIT_RIM5_RPE 0x08
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#define BIT_RIM5_RPS 0x04
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#define BIT_RIM5_RHWMS 0x02
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#define BIT_RIM5_RNES 0x01
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#define REG_RIM7 0xA6
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#define REG_RSCSE1 0xA8
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#define BITS_RSCSE1_ALL 0xFF
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#define BIT_RSCSE1_CH1 0x80
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#define BIT_RSCSE1_CH2 0x40
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#define BIT_RSCSE1_CH3 0x20
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#define BIT_RSCSE1_CH4 0x10
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#define BIT_RSCSE1_CH5 0x08
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#define BIT_RSCSE1_CH6 0x04
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#define BIT_RSCSE1_CH7 0x02
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#define BIT_RSCSE1_CH8 0x01
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#define REG_RSCSE2 0xA9
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#define BITS_RSCSE2_ALL 0xFF
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#define BIT_RSCSE2_CH9 0x80
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#define BIT_RSCSE2_CH10 0x40
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#define BIT_RSCSE2_CH11 0x20
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#define BIT_RSCSE2_CH12 0x10
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#define BIT_RSCSE2_CH13 0x08
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#define BIT_RSCSE2_CH14 0x04
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#define BIT_RSCSE2_CH15 0x02
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#define BIT_RSCSE2_CH16 0x01
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#define REG_RSCSE3 0xAA
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#define BITS_RSCSE3_ALL 0xFF
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#define BIT_RSCSE3_CH17 0x80
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#define BIT_RSCSE3_CH18 0x40
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#define BIT_RSCSE3_CH19 0x20
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#define BIT_RSCSE3_CH20 0x10
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#define BIT_RSCSE3_CH21 0x08
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#define BIT_RSCSE3_CH22 0x04
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#define BIT_RSCSE3_CH23 0x02
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#define BIT_RSCSE3_CH24 0x01
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#define REG_RSCSE4 0xAB
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#define BITS_RSCSE4_ALL 0xFF
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#define BIT_RSCSE4_CH25 0x80
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#define BIT_RSCSE4_CH26 0x40
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#define BIT_RSCSE4_CH27 0x20
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#define BIT_RSCSE4_CH28 0x10
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#define BIT_RSCSE4_CH29 0x08
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#define BIT_RSCSE4_CH30 0x04
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#define BIT_RSCSE4_CH31 0x02
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#define BIT_RSCSE4_CH32 0x01
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#define REG_RRTS1 0xB0
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#define BIT_RRTS1_RRAI 0x08
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#define BIT_RRTS1_RAIS 0x04
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#define BIT_RRTS1_RLOS 0x02
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#define BIT_RRTS1_RLOF 0x01
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#define REG_RRTS3 0xB2
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#define BIT_RRTS3_T1_LORC 0x08
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#define BIT_RRTS3_T1_LSP 0x08
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#define BIT_RRTS3_T1_LDN 0x02
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#define BIT_RRTS3_T1_LUP 0x01
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#define BIT_RRTS3_E1_LORC 0x08
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#define BIT_RRTS3_E1_V52LNK 0x02
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#define BIT_RRTS3_E1_RDMA 0x01
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#define REG_RGCCS1 0xCC
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#define REG_RGCCS2 0xCD
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#define REG_RGCCS3 0xCE
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#define REG_RGCCS4 0xCF
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#define REG_RCICE1 0xD0
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#define REG_RCICE2 0xD1
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#define REG_RCICE3 0xD2
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#define REG_RCICE4 0xD3
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/* TX Framer Register Definitions */
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#define REG_E1TSACR 0x114
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#define BIT_E1TSACR_SiAF 0x80
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#define BIT_E1TSACR_SiNAF 0x40
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#define BIT_E1TSACR_RA 0x20
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#define BIT_E1TSACR_Sa4 0x10
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#define BIT_E1TSACR_Sa5 0x08
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#define BIT_E1TSACR_Sa6 0x04
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#define BIT_E1TSACR_Sa7 0x02
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#define BIT_E1TSACR_Sa8 0x01
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#define REG_SSIE1 0x118
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#define BITS_SSIE1_ALL 0xFF
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#define BIT_SSIE1_CH1 0x80
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#define BIT_SSIE1_CH2 0x40
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#define BIT_SSIE1_CH3 0x20
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#define BIT_SSIE1_CH4 0x10
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#define BIT_SSIE1_CH5 0x08
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#define BIT_SSIE1_CH6 0x04
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#define BIT_SSIE1_CH7 0x02
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#define BIT_SSIE1_CH8 0x01
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#define REG_SSIE2 0x119
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#define BITS_SSIE2_ALL 0xFF
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#define BIT_SSIE2_CH9 0x80
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#define BIT_SSIE2_CH10 0x40
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#define BIT_SSIE2_CH11 0x20
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#define BIT_SSIE2_CH12 0x10
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#define BIT_SSIE2_CH13 0x08
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#define BIT_SSIE2_CH14 0x04
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#define BIT_SSIE2_CH15 0x02
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#define BIT_SSIE2_CH16 0x01
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#define REG_SSIE3 0x11A
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#define BITS_SSIE3_ALL 0xFF
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#define BIT_SSIE3_CH17 0x80
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#define BIT_SSIE3_CH18 0x40
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#define BIT_SSIE3_CH19 0x20
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#define BIT_SSIE3_CH20 0x10
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#define BIT_SSIE3_CH21 0x08
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#define BIT_SSIE3_CH22 0x04
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#define BIT_SSIE3_CH23 0x02
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#define BIT_SSIE3_CH24 0x01
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#define REG_SSIE4 0x11B
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#define BITS_SSIE4_ALL 0xFF
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#define BIT_SSIE4_CH25 0x80
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#define BIT_SSIE4_CH26 0x40
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#define BIT_SSIE4_CH27 0x20
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#define BIT_SSIE4_CH28 0x10
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#define BIT_SSIE4_CH29 0x08
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#define BIT_SSIE4_CH30 0x04
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#define BIT_SSIE4_CH31 0x02
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#define BIT_SSIE4_CH32 0x01
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#define REG_TS1 0x140
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#define BIT_TS_A 0x08
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#define BIT_TS_B 0x04
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#define BIT_TS_C 0x02
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#define BIT_TS_D 0x01
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#define REG_TS2 0x141
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#define REG_TS3 0x142
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#define REG_TS4 0x143
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#define REG_TS5 0x144
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#define REG_TS6 0x145
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#define REG_TS7 0x146
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#define REG_TS8 0x147
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#define REG_TS9 0x148
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#define REG_TS10 0x149
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#define REG_TS11 0x14A
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#define REG_TS12 0x14B
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#define REG_TS13 0x14C
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#define REG_TS14 0x14D
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#define REG_TS15 0x14E
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#define REG_TS16 0x14F
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#define REG_TCICE1 0x150
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#define REG_TCICE2 0x151
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#define REG_TCICE3 0x152
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#define REG_TCICE4 0x153
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#define REG_T1TFDL 0x162
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#define REG_E1TAF 0x164
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#define REG_E1TNAF 0x165
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#define REG_E1TSa4 0x169
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#define REG_E1TSa5 0x16A
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#define REG_E1TSa6 0x16B
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#define REG_E1TSa7 0x16C
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#define REG_E1TSa8 0x16D
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#define REG_TMMR 0x180
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#define BIT_TMMR_FRM_EN 0x80
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#define BIT_TMMR_INIT_DONE 0x40
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#define BIT_TMMR_SFTRST 0x02
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#define BIT_TMMR_T1E1 0x01
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#define REG_TCR1 0x181
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#define BIT_TCR1_T1_TJC 0x80
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#define BIT_TCR1_T1_TFPT 0x40
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#define BIT_TCR1_T1_TCPT 0x20
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#define BIT_TCR1_T1_TSSE 0x10
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#define BIT_TCR1_T1_GB7S 0x08
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#define BIT_TCR1_T1_TB8ZS 0x04
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#define BIT_TCR1_T1_TAIS 0x02
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#define BIT_TCR1_T1_TRAI 0x01
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#define BIT_TCR1_E1_TTPT 0x80
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#define BIT_TCR1_E1_T16S 0x40
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#define BIT_TCR1_E1_TG802 0x20
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#define BIT_TCR1_E1_TSiS 0x10
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#define BIT_TCR1_E1_TSA1 0x08
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#define BIT_TCR1_E1_THDB3 0x04
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#define BIT_TCR1_E1_TAIS 0x02
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#define BIT_TCR1_E1_TCRC4 0x01
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#define REG_TCR2 0x182
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#define BIT_TCR2_T1_TD4RM 0x04
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#define BIT_TCR2_T1_TSLC96 0x40
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#define BIT_TCR2_T1_TFDLS 0x80
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#define BIT_TCR2_E1_AEBE 0x80
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#define REG_TCR3 0x183
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#define BIT_TCR3_ODF 0x80
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#define BIT_TCR3_ODM 0x40
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#define BIT_TCR3_TCSS1 0x20
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#define BIT_TCR3_TCSS0 0x10
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#define BIT_TCR3_MFRS 0x08
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#define BIT_TCR3_TFM 0x04
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#define BIT_TCR3_IBPV 0x02
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#define BIT_TCR3_TLOOP 0x01
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#define REG_TIOCR 0x184
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#define BIT_TIOCR_TCLKINV 0x80
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#define BIT_TIOCR_TSYNCINV 0x40
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#define BIT_TIOCR_TSSYNCINV 0x20
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#define BIT_TIOCR_TSCLKM 0x10
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#define BIT_TIOCR_TSSM 0x08
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#define BIT_TIOCR_TSIO 0x04
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#define BIT_TIOCR_TSDW 0x02
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#define BIT_TIOCR_TSM 0x01
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#define REG_TESCR 0x185
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#define BIT_TESCR_TDATFMT 0x80
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#define BIT_TESCR_TGPCKEN 0x40
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#define BIT_TESCR_TESE 0x01
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#define REG_TLS1 0x190
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#define BIT_TLS1_TPDV 0x08
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#define BIT_TLS1_TMF 0x04
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#define BIT_TLS1_LOTCC 0x02
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#define BIT_TLS1_LOTC 0x01
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#define REG_TLS2 0x191
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#define REG_TLS3 0x192
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#define REG_TIIR 0x19F
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#define BIT_TIIR_TLS3 0x04
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#define BIT_TIIR_TLS2 0x02
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#define BIT_TIIR_TLS1 0x01
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#define REG_TIM1 0x1A0
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#define REG_TIM2 0x1A1
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#define REG_TIM3 0x1A2
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#define REG_TGCCS1 0x1CC
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#define REG_TGCCS2 0x1CD
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#define REG_TGCCS3 0x1CE
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#define REG_TGCCS4 0x1CF
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/* LIU Register Definitions */
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#define REG_LTRCR 0x1000
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#define BIT_LTRCR_JADS 0x10
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#define BIT_LTRCR_JAPS1 0x08
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#define BIT_LTRCR_JAPS0 0x04
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#define BIT_LTRCR_T1J1E1S 0x02
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#define BIT_LTRCR_LSC 0x01
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#define REG_LTITSR 0x1001
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#define BIT_LTITSR_TIMPTOFF 0x40
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#define BIT_LTITSR_TIMPL1 0x20
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#define BIT_LTITSR_TIMPL0 0x10
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#define BIT_LTITSR_L2 0x04
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#define BIT_LTITSR_L1 0x02
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#define BIT_LTITSR_L0 0x01
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#define REG_LMCR 0x1002
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#define BIT_LMCR_TAIS 0x80
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#define BIT_LMCR_ATAIS 0x40
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#define BIT_LMCR_LLB 0x20
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#define BIT_LMCR_ALB 0x10
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#define BIT_LMCR_RLB 0x08
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#define BIT_LMCR_TPDE 0x04
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#define BIT_LMCR_RPLDE 0x02
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#define BIT_LMCR_TE 0x01
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#define REG_LRSR 0x1003
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#define BIT_LRSR_OEQ 0x20
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#define BIT_LRSR_UEQ 0x10
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#define BIT_LRSR_SCS 0x04
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#define BIT_LRSR_OCS 0x02
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#define BIT_LRSR_LOSS 0x01
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#define REG_LSIMR 0x1004
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#define BIT_LSIMR_JALTCIM 0x80
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#define BIT_LSIMR_OCCIM 0x40
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#define BIT_LSIMR_SCCIM 0x20
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#define BIT_LSIMR_LOSCIM 0x10
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#define BIT_LSIMR_JALTSIM 0x08
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#define BIT_LSIMR_OCDIM 0x04
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#define BIT_LSIMR_SCDIM 0x02
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#define BIT_LSIMR_LOSDIM 0x01
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|
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#define REG_LLSR 0x1005
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#define BIT_LLSR_JALTC 0x80
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#define BIT_LLSR_OCC 0x40
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#define BIT_LLSR_SCC 0x20
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#define BIT_LLSR_LOSC 0x10
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#define BIT_LLSR_JALTS 0x08
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#define BIT_LLSR_OCD 0x04
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#define BIT_LLSR_SCD 0x03
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#define BIT_LLSR_LOSD 0x01
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|
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#define REG_LRSL 0x1006
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#define REG_LRSL_SHIFT 4
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#define REG_LRSL_MASK 0x0F
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#define BIT_LRSL_RSL3 0x80
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#define BIT_LRSL_RSL2 0x40
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#define BIT_LRSL_RSL1 0x20
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#define BIT_LRSL_RSL0 0x10
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|
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#define REG_LRISMR 0x1007
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#define BIT_LRISMR_RG703 0x80
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|
#define BIT_LRISMR_RIMPOFF 0x40
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#define BIT_LRISMR_RIMPM1 0x20
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#define BIT_LRISMR_RIMPM0 0x10
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#define BIT_LRISMR_RTR 0x08
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|
#define BIT_LRISMR_RMONEN 0x04
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|
#define BIT_LRISMR_RSMS1 0x02
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#define BIT_LRISMR_RSMS0 0x01
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|
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/* BERT Register Definitions */
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|
#define REG_BLSR 0x110E
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|
#define BIT_BLSR_BBED 0x40
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|
#define BIT_BLSR_BBCO 0x20
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|
#define BIT_BLSR_BECO 0x10
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|
#define BIT_BLSR_BRA1 0x08
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|
#define BIT_BLSR_BRA0 0x04
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#define BIT_BLSR_BRLOS 0x02
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#define BIT_BLSR_BSYNC 0x01
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#endif /* __SDLA_TE1_DS_H */
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