321 lines
11 KiB
C
321 lines
11 KiB
C
/*****************************************************************************
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* sdlasfm.h WANPIPE(tm) Multiprotocol WAN Link Driver.
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* Definitions for the SDLA Firmware Module (SFM).
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*
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* Author: Gideon Hack
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*
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* Copyright: (c) 1995-1999 Sangoma Technologies Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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* ============================================================================
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* Jun 02, 1999 Gideon Hack Added support for the S514 adapter.
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* Dec 11, 1996 Gene Kozin Cosmetic changes
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* Apr 16, 1996 Gene Kozin Changed adapter & firmware IDs. Version 2
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* Dec 15, 1995 Gene Kozin Structures chaned
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* Nov 09, 1995 Gene Kozin Initial version.
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*****************************************************************************/
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#ifndef _SDLASFM_H
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#define _SDLASFM_H
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/****** Defines *************************************************************/
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#define SFM_VERSION 2
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#define SFM_SIGNATURE "SFM - Sangoma SDLA Firmware Module"
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/* min/max */
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#define SFM_IMAGE_SIZE 0x8000 /* max size of SDLA code image file */
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#define SFM_DESCR_LEN 256 /* max length of description string */
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#define SFM_MAX_SDLA 16 /* max number of compatible adapters */
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/* Adapter types */
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#if defined(__WINDOWS__)
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#define INVALID_DEVICE_TYPE 0x0000
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#endif
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#define SDLA_S502A 5020
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#define SDLA_S502E 5021
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#define SDLA_S503 5030
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#define SDLA_S508 5080
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#define SDLA_S507 5070
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#define SDLA_S509 5090
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#define SDLA_S514 5140
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#define SDLA_ADSL 6000
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#define SDLA_AFT 7000
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/* S514 PCI adapter CPU numbers */
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#define S514_CPU_A 'A'
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#define S514_CPU_B 'B'
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#define SDLA_CPU_A 1
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#define SDLA_CPU_B 2
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#define SDLA_GET_CPU(cpu_no) (cpu_no==SDLA_CPU_A)?S514_CPU_A:S514_CPU_B
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/* Firmware identification numbers:
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* 0 .. 999 Test & Diagnostics
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* 1000 .. 1999 Streaming HDLC
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* 2000 .. 2999 Bisync
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* 3000 .. 3999 SDLC
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* 4000 .. 4999 HDLC
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* 5000 .. 5999 X.25
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* 6000 .. 6999 Frame Relay
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* 7000 .. 7999 PPP
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* 8000 .. 8999 Cisco HDLC
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*/
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#define SFID_CALIB502 200
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#define SFID_STRM502 1200
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#define SFID_STRM508 1800
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#define SFID_BSC502 2200
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#define SFID_BSCMP514 2201
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#define SFID_SDLC502 3200
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#define SFID_HDLC502 4200
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#define SFID_HDLC508 4800
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#define SFID_X25_502 5200
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#define SFID_X25_508 5800
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#define SFID_FR502 6200
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#define SFID_FR508 6800
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#define SFID_PPP502 7200
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#define SFID_PPP508 7800
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#define SFID_PPP514 7140
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#define SFID_CHDLC508 8800
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#define SFID_CHDLC514 8140
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#define SFID_BITSTRM 10000
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#define SFID_EDU_KIT 8141
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#define SFID_SS7514 9000
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#define SFID_BSCSTRM 2205
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#define SFID_ADSL 20000
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#define SFID_SDLC514 3300
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#define SFID_ATM 11000
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#define SFID_POS 12000
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#define SFID_ADCCP 13000
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#define SFID_AFT 30000
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/****** Data Types **********************************************************/
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typedef struct sfm_info /* firmware module information */
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{
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unsigned short codeid; /* firmware ID */
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unsigned short version; /* firmaware version number */
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unsigned short adapter[SFM_MAX_SDLA]; /* compatible adapter types */
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unsigned int memsize; /* minimum memory size */
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unsigned short reserved[2]; /* reserved */
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unsigned short startoffs; /* entry point offset */
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unsigned short winoffs; /* dual-port memory window offset */
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unsigned short codeoffs; /* code load offset */
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unsigned short codesize; /* code size */
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unsigned short dataoffs; /* configuration data load offset */
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unsigned short datasize; /* configuration data size */
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} sfm_info_t;
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typedef struct sfm /* SDLA firmware file structire */
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{
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char signature[80]; /* SFM file signature */
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unsigned short version; /* file format version */
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unsigned short checksum; /* info + image */
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unsigned short reserved[6]; /* reserved */
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char descr[SFM_DESCR_LEN]; /* description string */
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sfm_info_t info; /* firmware module info */
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unsigned char image[1]; /* code image (variable size) */
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} sfm_t;
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/* settings for the 'adapter_type' */
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#define S5141_ADPTR_1_CPU_SERIAL 0x0011 /* S5141, single CPU, serial */
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#define S5142_ADPTR_2_CPU_SERIAL 0x0012 /* S5142, dual CPU, serial */
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#define S5143_ADPTR_1_CPU_FT1 0x0013 /* S5143, single CPU, FT1 */
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#define S5144_ADPTR_1_CPU_T1E1 0x0014 /* S5144, single CPU, T1/E1 */
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#define S5145_ADPTR_1_CPU_56K 0x0015 /* S5145, single CPU, 56K */
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#define S5147_ADPTR_2_CPU_T1E1 0x0017 /* S5147, dual CPU, T1/E1 */
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#define S5148_ADPTR_1_CPU_T1E1 0x0018 /* S5148, single CPU, T1/E1 */
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#define S518_ADPTR_1_CPU_ADSL 0x0018 /* S518, adsl card */
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#define A101_ADPTR_TE1_MASK 0x0040 /* Single T1/E1 type mask */
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#define A101_ADPTR_1TE1 0x0041 /* 1 Channel T1/E1 */
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#define A101_ADPTR_2TE1 0x0042 /* 2 Channels T1/E1 */
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#define A104_ADPTR_TE1_MASK 0x0080 /* Quad T1/E1 type mask */
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#define A104_ADPTR_4TE1 0x0081 /* Quad line T1/E1 */
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#define A104_ADPTR_4TE1_PCIX 0x0082 /* Quad line T1/E1 PCI Express */
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#define A108_ADPTR_TE1_MASK 0x0200 /* 8 Channels T1/E1 type mask */
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#define A108_ADPTR_8TE1 0x0201 /* 8 Channels T1/E1 */
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#define A100_ADPTR_T3E3_MASK 0x0100 /* T3/E3 type mask */
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#define A100_ADPTR_U_1TE3 0x0101 /* 1 Channel T3/E3 (Proto) */
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#define A300_ADPTR_U_1TE3 0x0102 /* 1 Channel T3/E3 (unchannelized) */
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#define A305_ADPTR_C_1TE3 0x0104 /* 1 Channel T3/E3 (channelized) */
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#define A200_ADPTR_ANALOG_MASK 0x0400 /* AFT-200 REMORA analog board mask */
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#define A200_ADPTR_ANALOG 0x0401 /* AFT-200 REMORA analog board */
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#define A400_ADPTR_ANALOG_MASK 0x0800 /* AFT-400 REMORA analog board mask */
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#define A400_ADPTR_ANALOG 0x0801 /* AFT-400 REMORA analog board */
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#define AFT_ADPTR_ISDN_MASK 0x1000 /* AFT ISDN BRI board mask */
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#define AFT_ADPTR_ISDN 0x1001 /* AFT ISDN BRI board */
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#define AFT_ADPTR_56K_MASK 0x2000 /* AFT 56K board mask */
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#define AFT_ADPTR_56K 0x2001 /* AFT 56K board */
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#define OPERATE_T1E1_AS_SERIAL 0x8000 /* For bitstreaming only
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* Allow the applicatoin to
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* E1 front end */
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/* settings for the 'adapter_subtype' */
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#define AFT_SUBTYPE_NORMAL 0x00
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#define AFT_SUBTYPE_SHARK 0x01
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#define IS_ADPTR_SHARK(type) ((type) == AFT_SUBTYPE_SHARK)
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/* settings for the 'adapter_security' */
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#define AFT_SECURITY_NONE 0x00
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#define AFT_SECURITY_CHAN 0x01
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#define AFT_SECURITY_UNCHAN 0x02
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/* settings for the 'adptr_subtype' */
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#define AFT_SUBTYPE_SHIFT 8
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#define AFT_SUBTYPE_MASK 0x0F
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/* CPLD interface */
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#define AFT_MCPU_INTERFACE_ADDR 0x46
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#define AFT_MCPU_INTERFACE 0x44
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#define AFT56K_MCPU_INTERFACE_ADDR 0x46
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#define AFT56K_MCPU_INTERFACE 0x44
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/* CPLD definitions */
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#define AFT_SECURITY_1LINE_UNCH 0x00
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#define AFT_SECURITY_1LINE_CH 0x01
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#define AFT_SECURITY_2LINE_UNCH 0x02
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#define AFT_SECURITY_2LINE_CH 0x03
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#define AFT_BIT_DEV_ADDR_CLEAR 0x600
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#define AFT_BIT_DEV_ADDR_CPLD 0x200
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#define AFT4_BIT_DEV_ADDR_CLEAR 0x800
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#define AFT4_BIT_DEV_ADDR_CPLD 0x800
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#define AFT56K_BIT_DEV_ADDR_CPLD 0x800
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/* Maxim CPLD definitions */
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#define AFT8_BIT_DEV_ADDR_CLEAR 0x1800 /* QUAD */
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#define AFT8_BIT_DEV_ADDR_CPLD 0x800
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#define AFT8_BIT_DEV_MAXIM_ADDR_CPLD 0x1000
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#define AFT3_BIT_DEV_ADDR_EXAR_CLEAR 0x600
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#define AFT3_BIT_DEV_ADDR_EXAR_CPLD 0x400
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#define AFT_SECURITY_CPLD_REG 0x09
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#define AFT_SECURITY_CPLD_SHIFT 0x02
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#define AFT_SECURITY_CPLD_MASK 0x03
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/* AFT SHARK CPLD */
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#define AFT_SH_CPLD_BOARD_CTRL_REG 0x00
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#define AFT_SH_CPLD_BOARD_STATUS_REG 0x01
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#define A200_SH_CPLD_BOARD_STATUS_REG 0x09
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#define AFT_SH_SECURITY_MASK 0x07
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#define AFT_SH_SECURITY_SHIFT 1
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#define AFT_SH_SECURITY(reg) \
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(((reg) >> AFT_SH_SECURITY_SHIFT) & AFT_SH_SECURITY_MASK)
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#define A104_SECURITY_32_ECCHAN 0x00
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#define A104_SECURITY_64_ECCHAN 0x01
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#define A104_SECURITY_96_ECCHAN 0x02
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#define A104_SECURITY_128_ECCHAN 0x03
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#define A104_SECURITY_256_ECCHAN 0x04
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#define A104_SECURITY_PROTO_128_ECCHAN 0x05
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#define A104_SECURITY_0_ECCHAN 0x07
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#define A108_SECURITY_32_ECCHAN 0x00
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#define A108_SECURITY_64_ECCHAN 0x01
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#define A108_SECURITY_96_ECCHAN 0x02
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#define A108_SECURITY_128_ECCHAN 0x03
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#define A108_SECURITY_256_ECCHAN 0x04
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#define A108_SECURITY_0_ECCHAN 0x05
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#define A104_ECCHAN(val) \
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((val) == A104_SECURITY_32_ECCHAN) ? 32 : \
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((val) == A104_SECURITY_64_ECCHAN) ? 64 : \
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((val) == A104_SECURITY_96_ECCHAN) ? 96 : \
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((val) == A104_SECURITY_128_ECCHAN) ? 128 : \
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((val) == A104_SECURITY_PROTO_128_ECCHAN) ? 128 : \
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((val) == A104_SECURITY_256_ECCHAN) ? 256 : 0
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#define A108_ECCHAN(val) \
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((val) == A108_SECURITY_32_ECCHAN) ? 32 : \
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((val) == A108_SECURITY_64_ECCHAN) ? 64 : \
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((val) == A108_SECURITY_96_ECCHAN) ? 96 : \
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((val) == A108_SECURITY_128_ECCHAN) ? 128 : \
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((val) == A108_SECURITY_256_ECCHAN) ? 256 : 0
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#define AFT_RM_SECURITY_16_ECCHAN 0x00
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#define AFT_RM_SECURITY_32_ECCHAN 0x01
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#define AFT_RM_SECURITY_0_ECCHAN 0x05
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#define AFT_RM_ECCHAN(val) \
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((val) == AFT_RM_SECURITY_16_ECCHAN) ? 16 : \
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((val) == AFT_RM_SECURITY_32_ECCHAN) ? 32 : 0
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#define SDLA_ADPTR_NAME(adapter_type) \
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(adapter_type == S5141_ADPTR_1_CPU_SERIAL) ? "S514-1-PCI" : \
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(adapter_type == S5142_ADPTR_2_CPU_SERIAL) ? "S514-2-PCI" : \
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(adapter_type == S5143_ADPTR_1_CPU_FT1) ? "S514-3-PCI" : \
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(adapter_type == S5144_ADPTR_1_CPU_T1E1) ? "S514-4-PCI" : \
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(adapter_type == S5145_ADPTR_1_CPU_56K) ? "S514-5-PCI" : \
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(adapter_type == S5147_ADPTR_2_CPU_T1E1) ? "S514-7-PCI" : \
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(adapter_type == S518_ADPTR_1_CPU_ADSL) ? "S518-PCI" : \
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(adapter_type == A101_ADPTR_1TE1) ? "AFT-A101" : \
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(adapter_type == A101_ADPTR_2TE1) ? "AFT-A102" : \
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(adapter_type == A104_ADPTR_4TE1) ? "AFT-A104" : \
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(adapter_type == A108_ADPTR_8TE1) ? "AFT-A108" : \
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(adapter_type == A300_ADPTR_U_1TE3) ? "AFT-A301" : \
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(adapter_type == A200_ADPTR_ANALOG) ? "AFT-A200" : \
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(adapter_type == A400_ADPTR_ANALOG) ? "AFT-A400" : \
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(adapter_type == AFT_ADPTR_56K) ? "AFT-A056" : \
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"UNKNOWN"
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#if 0
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#define SDLA_ADPTR_DECODE(adapter_type) \
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(adapter_type == S5141_ADPTR_1_CPU_SERIAL) ? "S514-1-PCI" : \
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(adapter_type == S5142_ADPTR_2_CPU_SERIAL) ? "S514-2-PCI" : \
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(adapter_type == S5143_ADPTR_1_CPU_FT1) ? "S514-3-PCI" : \
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(adapter_type == S5144_ADPTR_1_CPU_T1E1) ? "S514-4-PCI" : \
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(adapter_type == S5145_ADPTR_1_CPU_56K) ? "S514-5-PCI" : \
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(adapter_type == S5147_ADPTR_2_CPU_T1E1) ? "S514-7-PCI" : \
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(adapter_type == S518_ADPTR_1_CPU_ADSL) ? "S518-PCI " : \
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(adapter_type == A101_ADPTR_1TE1) ? "AFT-A101 " : \
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(adapter_type == A101_ADPTR_2TE1) ? "AFT-A102 " : \
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(adapter_type == A104_ADPTR_4TE1) ? "AFT-A104 " : \
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(adapter_type == A300_ADPTR_U_1TE3) ? "AFT-A301 " : \
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"UNKNOWN "
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#endif
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#define AFT_GET_SECURITY(security) \
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((security >> AFT_SECURITY_CPLD_SHIFT) & AFT_SECURITY_CPLD_MASK)
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#define AFT_SECURITY(adapter_security) \
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(adapter_security == AFT_SECURITY_CHAN) ? "c" : \
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(adapter_security == AFT_SECURITY_UNCHAN) ? "u" : ""
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#define AFT_SECURITY_DECODE(adapter_security) \
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(adapter_security == AFT_SECURITY_CHAN) ? "Channelized" : \
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(adapter_security == AFT_SECURITY_UNCHAN) ? "Unchannelized" : ""
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#define AFT_SUBTYPE(adptr_subtype) \
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(adptr_subtype == AFT_SUBTYPE_NORMAL) ? "" : \
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(adptr_subtype == AFT_SUBTYPE_SHARK) ? "-SH" : ""
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#define AFT_SUBTYPE_DECODE(adptr_subtype) \
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(adptr_subtype == AFT_SUBTYPE_NORMAL) ? "" : \
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(adptr_subtype == AFT_SUBTYPE_SHARK) ? "SHARK" : ""
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#define AFT_PCIEXPRESS_DECODE(hwcard) \
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((hwcard)->pci_bridge_dev) ? " PCI-Express" : ""
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#endif /* _SDLASFM_H */
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