827 lines
21 KiB
C
827 lines
21 KiB
C
/*****************************************************************************
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* aft_aft_analog.c
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*
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* WANPIPE(tm) AFT A104 Hardware Support
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*
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* Authors: Nenad Corbic <ncorbic@sangoma.com>
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*
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* Copyright: (c) 2003-2005 Sangoma Technologies Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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* ============================================================================
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* Sep 25, 2005 Nenad Corbic Initial Version
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*****************************************************************************/
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__OpenBSD__)
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# include <wanpipe_includes.h>
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# include <wanpipe.h>
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# include <wanpipe_abstr.h>
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# include <if_wanpipe_common.h> /* Socket Driver common area */
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# include <sdlapci.h>
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# include <sdla_aft_te1.h>
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# include <wanpipe_iface.h>
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# include <sdla_remora.h>
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#elif defined(__WINDOWS__)
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# include <wanpipe_includes.h>
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# include <wanpipe.h>
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# include <if_wanpipe_common.h> /* Socket Driver common area */
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# include <sdlapci.h>
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# include <sdla_aft_te1.h>
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# include <wanpipe_iface.h>
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# include <wanpipe_tdm_api.h>
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# include <sdla_remora.h>
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#else
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# include <linux/wanpipe_includes.h>
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# include <linux/wanpipe_defines.h>
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# include <linux/wanpipe.h>
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# include <linux/wanproc.h>
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# include <linux/wanpipe_abstr.h>
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# include <linux/if_wanpipe_common.h> /* Socket Driver common area */
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# include <linux/if_wanpipe.h>
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# include <linux/sdlapci.h>
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//# include <linux/sdla_ec.h>
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# include <linux/sdla_aft_te1.h>
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# include <linux/wanpipe_iface.h>
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# include <linux/wanpipe_tdm_api.h>
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# include <linux/sdla_remora.h>
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#endif
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/*==============================================
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* PRIVATE FUNCITONS
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*
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*/
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#if defined(CONFIG_WANPIPE_HWEC)
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static int aft_analog_hwec_reset(void *pcard, int reset);
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static int aft_analog_hwec_enable(void *pcard, int enable, int fe_chan);
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#endif
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static int aft_map_fifo_baddr_and_size(sdla_t *card, unsigned char fifo_size, unsigned char *addr);
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static char fifo_size_vector[] = {1, 2, 4, 8, 16, 32};
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static char fifo_code_vector[] = {0, 1, 3, 7,0xF,0x1F};
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static int request_fifo_baddr_and_size(sdla_t *card, private_area_t *chan)
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{
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unsigned char req_fifo_size,fifo_size;
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int i;
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/* Calculate the optimal fifo size based
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* on the number of time slots requested */
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req_fifo_size = 1;
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DEBUG_TEST("%s:%s: Optimal Fifo Size =%d Timeslots=%d \n",
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card->devname,chan->if_name,req_fifo_size,chan->num_of_time_slots);
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fifo_size=(unsigned char)aft_map_fifo_baddr_and_size(card,req_fifo_size,&chan->fifo_base_addr);
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if (fifo_size == 0 || chan->fifo_base_addr == 31){
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DEBUG_EVENT("%s:%s: Error: Failed to obtain fifo size %d or addr %d \n",
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card->devname,chan->if_name,fifo_size,chan->fifo_base_addr);
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return -EINVAL;
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}
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DEBUG_TEST("%s:%s: Optimal Fifo Size =%d Timeslots=%d New Fifo Size=%d \n",
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card->devname,chan->if_name,req_fifo_size,chan->num_of_time_slots,fifo_size);
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for (i=0;i<sizeof(fifo_size_vector);i++){
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if (fifo_size_vector[i] == fifo_size){
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chan->fifo_size_code=fifo_code_vector[i];
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break;
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}
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}
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if (fifo_size != req_fifo_size){
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DEBUG_EVENT("%s:%s: Warning: Failed to obtain the req fifo %d got %d\n",
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card->devname,chan->if_name,req_fifo_size,fifo_size);
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}
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DEBUG_TEST("%s: %s:Fifo Size=%d Timeslots=%d Fifo Code=%d Addr=%d\n",
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card->devname,chan->if_name,fifo_size,
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chan->num_of_time_slots,chan->fifo_size_code,
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chan->fifo_base_addr);
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chan->fifo_size = fifo_size;
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return 0;
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}
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static int aft_map_fifo_baddr_and_size(sdla_t *card, unsigned char fifo_size, unsigned char *addr)
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{
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u32 reg=0;
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u8 i;
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for (i=0;i<fifo_size;i++){
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wan_set_bit(i,®);
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}
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DEBUG_TEST("%s: Trying to MAP 0x%X to 0x%lX\n",
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card->devname,reg,card->u.aft.fifo_addr_map);
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for (i=0;i<32;i+=fifo_size){
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if (card->u.aft.fifo_addr_map & (reg<<i)){
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continue;
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}
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card->u.aft.fifo_addr_map |= reg<<i;
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*addr=i;
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DEBUG_TEST("%s: Card fifo Map 0x%lX Addr =%d\n",
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card->devname,card->u.aft.fifo_addr_map,i);
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return fifo_size;
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}
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if (fifo_size == 1){
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return 0;
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}
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fifo_size = fifo_size >> 1;
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return aft_map_fifo_baddr_and_size(card,fifo_size,addr);
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}
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static int aft_free_fifo_baddr_and_size (sdla_t *card, private_area_t *chan)
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{
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u32 reg=0;
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int i;
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for (i=0;i<chan->fifo_size;i++){
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wan_set_bit(i,®);
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}
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DEBUG_TEST("%s: Unmapping 0x%X from 0x%lX\n",
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card->devname,reg<<chan->fifo_base_addr, card->u.aft.fifo_addr_map);
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card->u.aft.fifo_addr_map &= ~(reg<<chan->fifo_base_addr);
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DEBUG_TEST("%s: New Map is 0x%lX\n",
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card->devname, card->u.aft.fifo_addr_map);
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chan->fifo_size=0;
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chan->fifo_base_addr=0;
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return 0;
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}
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static char aft_request_logical_channel_num (sdla_t *card, private_area_t *chan)
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{
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signed char logic_ch=-1;
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int err;
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long i;
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int timeslots=0;
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DEBUG_TEST("-- Request_Xilinx_logic_channel_num:--\n");
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DEBUG_TEST("%s:%d Global Num Timeslots=%d Global Logic ch Map 0x%lX \n",
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__FUNCTION__,__LINE__,
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card->u.aft.num_of_time_slots,
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card->u.aft.logic_ch_map);
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/* Check that the time slot is not being used. If it is
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* stop the interface setup. Notice, though we proceed
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* to check for all timeslots before we start binding
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* the channels in. This way, we don't have to go back
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* and clean the time_slot_map */
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for (i=0;i<card->u.aft.num_of_time_slots;i++){
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if (wan_test_bit(i,&chan->time_slot_map)){
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if (chan->first_time_slot == -1){
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DEBUG_EVENT("%s: First TSlot :%ld\n",
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card->devname,i);
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chan->first_time_slot=i;
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}
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chan->last_time_slot=i;
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DEBUG_CFG("%s: Configuring %s for timeslot %ld\n",
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card->devname, chan->if_name,i+1);
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if (wan_test_bit(i,&card->u.aft.time_slot_map)){
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DEBUG_EVENT("%s: Channel/Time Slot resource conflict!\n",
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card->devname);
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DEBUG_EVENT("%s: %s: Channel/Time Slot %ld, aready in use!\n",
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card->devname,chan->if_name,(i+1));
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return -EEXIST;
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}
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timeslots++;
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}
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}
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if (timeslots > 1){
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DEBUG_EVENT("%s: Error: Analog Interface can only support a single timeslot\n",
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card->devname);
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chan->first_time_slot = -1;
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return -1;
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}
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err=request_fifo_baddr_and_size(card,chan);
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if (err){
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return -1;
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}
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logic_ch = (signed char)chan->first_time_slot;
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if (wan_test_and_set_bit(logic_ch,&card->u.aft.logic_ch_map)){
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return -1;
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}
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if (logic_ch == -1){
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return logic_ch;
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}
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for (i=0;i<card->u.aft.num_of_time_slots;i++){
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if (!wan_test_bit(i,&card->u.aft.logic_ch_map)){
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break;
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}
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}
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if (card->u.aft.dev_to_ch_map[(unsigned char)logic_ch]){
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DEBUG_EVENT("%s: Error, request logical ch=%d map busy\n",
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card->devname,logic_ch);
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return -1;
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}
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card->u.aft.dev_to_ch_map[(unsigned char)logic_ch]=(void*)chan;
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if (logic_ch >= card->u.aft.top_logic_ch){
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card->u.aft.top_logic_ch=logic_ch;
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aft_dma_max_logic_ch(card);
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}
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DEBUG_TEST("Binding logic ch %d Ptr=%p\n",logic_ch,chan);
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return logic_ch;
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}
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/*==============================================
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* PUBLIC FUNCITONS
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*
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*/
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int aft_analog_test_sync(sdla_t *card, int tx_only)
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{
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volatile int i,err=1;
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u32 reg;
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card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG), ®);
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if (wan_test_bit(AFT_LCFG_FE_IFACE_RESET_BIT,®)){
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DEBUG_EVENT("%s: Warning: Analog Reset Enabled %d! \n",
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card->devname, card->wandev.comm_port+1);
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}
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for (i=0;i<500;i++){
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card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG), ®);
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if (tx_only){
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if (wan_test_bit(AFT_LCFG_TX_FE_SYNC_STAT_BIT,®)){
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err=-EINVAL;
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WP_DELAY(200);
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}else{
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err=0;
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break;
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}
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}else{
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if (wan_test_bit(AFT_LCFG_TX_FE_SYNC_STAT_BIT,®) ||
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wan_test_bit(AFT_LCFG_RX_FE_SYNC_STAT_BIT,®)){
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err=-EINVAL;
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WP_DELAY(200);
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}else{
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err=0;
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break;
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}
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}
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}
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DEBUG_TEST("%s: DELAY INDEX = %i\n",
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card->devname,i);
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return err;
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}
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int aft_analog_led_ctrl(sdla_t *card, int color, int led_pos, int on)
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{
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/* NO LED ON ANALOG CARD */
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return 0;
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}
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int aft_analog_global_chip_config(sdla_t *card)
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{
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u32 reg;
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int err;
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/*============ GLOBAL CHIP CONFIGURATION ===============*/
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card->hw_iface.bus_read_4(card->hw,AFT_CHIP_CFG_REG, ®);
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/* Enable the chip/hdlc reset condition */
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reg=0;
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wan_set_bit(AFT_CHIPCFG_SFR_EX_BIT,®);
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wan_set_bit(AFT_CHIPCFG_SFR_IN_BIT,®);
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if (WAN_FE_NETWORK_SYNC(&card->fe)){ /*card->fe.fe_cfg.cfg.remora.network_sync*/
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DEBUG_EVENT("%s: Analog Clock set to Network Sync!\n",
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card->devname);
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wan_set_bit(AFT_CHIPCFG_ANALOG_CLOCK_SELECT_BIT,®);
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}
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DEBUG_CFG("--- AFT Chip Reset. -- \n");
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card->hw_iface.bus_write_4(card->hw,AFT_CHIP_CFG_REG,reg);
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WP_DELAY(10);
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/* Disable the chip/hdlc reset condition */
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wan_clear_bit(AFT_CHIPCFG_SFR_EX_BIT,®);
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wan_clear_bit(AFT_CHIPCFG_SFR_IN_BIT,®);
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wan_clear_bit(AFT_CHIPCFG_FE_INTR_CFG_BIT,®);
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#if 0
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wan_set_bit(AFT_CHIPCFG_SPI_SLOW_BIT,®);
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#endif
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DEBUG_CFG("--- Chip enable/config. -- \n");
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card->hw_iface.bus_write_4(card->hw,AFT_CHIP_CFG_REG,reg);
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/* Set Octasic reset */
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aft_analog_write_cpld(card, 0x00, 0x00);
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DEBUG_EVENT("%s: Global Front End Configuraton!\n",card->devname);
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err = -EINVAL;
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if (card->wandev.fe_iface.config){
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err = card->wandev.fe_iface.config(&card->fe);
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}
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if (err){
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DEBUG_EVENT("%s: Failed Front End configuration!\n",
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card->devname);
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return -EINVAL;
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}
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/* Run rest of initialization not from lock */
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if (card->wandev.fe_iface.post_init){
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err=card->wandev.fe_iface.post_init(&card->fe);
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}
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DEBUG_EVENT("%s: Remora config done!\n",card->devname);
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/* Enable global front end interrupt */
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__aft_fe_intr_ctrl(card, 1);
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return 0;
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}
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int aft_analog_global_chip_unconfig(sdla_t *card)
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{
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u32 reg=0;
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if (card->wandev.fe_iface.unconfig){
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card->wandev.fe_iface.unconfig(&card->fe);
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}
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/* Set Octasic to reset */
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#if 0
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aft_analog_write_cpld(card, 0x00, 0x00);
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#endif
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/* Disable the chip/hdlc reset condition */
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wan_set_bit(AFT_CHIPCFG_SFR_EX_BIT,®);
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wan_set_bit(AFT_CHIPCFG_SFR_IN_BIT,®);
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card->hw_iface.bus_write_4(card->hw,AFT_CHIP_CFG_REG,reg);
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return 0;
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}
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int aft_analog_chip_config(sdla_t *card, wandev_conf_t *conf)
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{
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u32 reg=0;
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int err=0;
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card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG), ®);
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if (!wan_test_bit(AFT_LCFG_FE_IFACE_RESET_BIT,®)){
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DEBUG_EVENT("%s: Error: Physical Port %i is busy! \n",
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card->devname, card->wandev.comm_port+1);
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return -EBUSY;
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}
|
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|
|
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/*============ LINE/PORT CONFIG REGISTER ===============*/
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card->hw_iface.bus_read_4(card->hw,
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AFT_PORT_REG(card,AFT_LINE_CFG_REG),®);
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wan_set_bit(AFT_LCFG_FE_IFACE_RESET_BIT,®);
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card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),reg);
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WP_DELAY(10);
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wan_clear_bit(AFT_LCFG_FE_IFACE_RESET_BIT,®);
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card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),reg);
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|
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WP_DELAY(10);
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|
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err=aft_analog_test_sync(card,1);
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|
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card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),®);
|
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if (err != 0){
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DEBUG_EVENT("%s: Error: Front End Interface Not Ready (0x%08X)!\n",
|
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card->devname,reg);
|
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return err;
|
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} else{
|
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DEBUG_EVENT("%s: Front End Interface Ready 0x%08X\n",
|
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card->devname,reg);
|
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}
|
|
|
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/* Enable Octasic Chip */
|
|
if (card->adptr_subtype == AFT_SUBTYPE_SHARK){
|
|
u16 max_ec_chans, max_ports_no;
|
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u32 cfg_reg, fe_port_map;
|
|
|
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card->hw_iface.getcfg(card->hw, SDLA_HWEC_NO, &max_ec_chans);
|
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card->hw_iface.getcfg(card->hw, SDLA_PORTS_NO, &max_ports_no);
|
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card->hw_iface.getcfg(card->hw, SDLA_PORT_MAP, &fe_port_map);
|
|
|
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card->hw_iface.bus_read_4(card->hw,AFT_CHIP_CFG_REG, &cfg_reg);
|
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if (max_ec_chans > aft_chipcfg_get_a200_ec_channels(cfg_reg)){
|
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DEBUG_EVENT(
|
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"%s: Critical Error: Exceeded Maximum Available Echo Channels!\n",
|
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card->devname);
|
|
DEBUG_EVENT(
|
|
"%s: Critical Error: Max Allowed=%d Configured=%d (%X)\n",
|
|
card->devname,
|
|
aft_chipcfg_get_a200_ec_channels(cfg_reg),
|
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max_ec_chans,
|
|
cfg_reg);
|
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return -EINVAL;
|
|
}
|
|
|
|
if (max_ec_chans){
|
|
#if defined(CONFIG_WANPIPE_HWEC)
|
|
card->wandev.ec_dev = wanpipe_ec_register(
|
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card,
|
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fe_port_map,
|
|
max_ports_no,
|
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max_ec_chans,
|
|
(void*)&conf->oct_conf);
|
|
card->wandev.hwec_reset = aft_analog_hwec_reset;
|
|
card->wandev.hwec_enable = aft_analog_hwec_enable;
|
|
#else
|
|
DEBUG_EVENT("%s: Wanpipe HW Echo Canceller modele is not compiled!\n",
|
|
card->devname);
|
|
#endif
|
|
}else{
|
|
DEBUG_EVENT(
|
|
"%s: WARNING: No Echo Canceller channels are available!\n",
|
|
card->devname);
|
|
}
|
|
}
|
|
|
|
|
|
/* Enable only Front End Interrupt
|
|
* Wait for front end to come up before enabling DMA */
|
|
card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG), ®);
|
|
wan_clear_bit(AFT_LCFG_DMA_INTR_BIT,®);
|
|
wan_clear_bit(AFT_LCFG_FIFO_INTR_BIT,®);
|
|
wan_clear_bit(AFT_LCFG_TDMV_INTR_BIT,®);
|
|
|
|
card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG), reg);
|
|
card->u.aft.lcfg_reg=reg;
|
|
|
|
aft_analog_led_ctrl(card, WAN_AFT_RED, 0,WAN_AFT_ON);
|
|
aft_analog_led_ctrl(card, WAN_AFT_GREEN, 0, WAN_AFT_OFF);
|
|
|
|
|
|
/*============ DMA CONTROL REGISTER ===============*/
|
|
|
|
/* Disable Global DMA because we will be
|
|
* waiting for the front end to come up */
|
|
reg=0;
|
|
aft_dmactrl_set_max_logic_ch(®,0);
|
|
wan_clear_bit(AFT_DMACTRL_GLOBAL_INTR_BIT,®);
|
|
card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_DMA_CTRL_REG),reg);
|
|
|
|
|
|
|
|
|
|
/*============ ENABLE MUX ==================*/
|
|
|
|
reg=0; /* 0xFFFFFFFF; */
|
|
card->hw_iface.bus_write_4(card->hw,AFT_ANALOG_DATA_MUX_CTRL_REG,reg);
|
|
|
|
|
|
aft_wdt_reset(card);
|
|
#if 0
|
|
/*FIXME: NC Dont need watchdog */
|
|
aft_wdt_set(card,AFT_WDTCTRL_TIMEOUT);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aft_analog_chip_unconfig(sdla_t *card)
|
|
{
|
|
u32 reg=0;
|
|
|
|
aft_wdt_reset(card);
|
|
|
|
/* Disable Octasic Chip */
|
|
if (card->adptr_subtype == AFT_SUBTYPE_SHARK){
|
|
if (card->wandev.ec_dev){
|
|
#if defined(CONFIG_WANPIPE_HWEC)
|
|
wanpipe_ec_unregister(card->wandev.ec_dev, card);
|
|
#else
|
|
DEBUG_EVENT(
|
|
"%s: Wanpipe HW Echo Canceller modele is not compiled!\n",
|
|
card->devname);
|
|
#endif
|
|
}
|
|
card->wandev.hwec_enable = NULL;
|
|
card->wandev.ec_dev = NULL;
|
|
}
|
|
|
|
wan_set_bit(AFT_LCFG_FE_IFACE_RESET_BIT,®);
|
|
card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aft_analog_chan_dev_config(sdla_t *card, void *chan_ptr)
|
|
{
|
|
u32 reg;
|
|
private_area_t *chan = (private_area_t*)chan_ptr;
|
|
u32 dma_ram_reg;
|
|
|
|
|
|
chan->logic_ch_num=aft_request_logical_channel_num(card, chan);
|
|
if (chan->logic_ch_num == -1){
|
|
return -EBUSY;
|
|
}
|
|
|
|
dma_ram_reg=AFT_PORT_REG(card,AFT_DMA_CHAIN_RAM_BASE_REG);
|
|
dma_ram_reg+=(chan->logic_ch_num*4);
|
|
|
|
reg=0;
|
|
card->hw_iface.bus_write_4(card->hw, dma_ram_reg, reg);
|
|
|
|
card->hw_iface.bus_read_4(card->hw, dma_ram_reg, ®);
|
|
|
|
aft_dmachain_set_fifo_size(®, chan->fifo_size_code);
|
|
aft_dmachain_set_fifo_base(®, chan->fifo_base_addr);
|
|
|
|
/* Initially always disable rx synchronization */
|
|
wan_clear_bit(AFT_DMACHAIN_RX_SYNC_BIT,®);
|
|
|
|
if (chan->channelized_cfg && !chan->hdlc_eng){
|
|
aft_dmachain_enable_tdmv_and_mtu_size(®,chan->mru);
|
|
}
|
|
|
|
card->hw_iface.bus_write_4(card->hw, dma_ram_reg, reg);
|
|
|
|
reg=0;
|
|
|
|
if (chan->channelized_cfg && !chan->hdlc_eng){
|
|
|
|
card->hw_iface.bus_read_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),®);
|
|
aft_lcfg_tdmv_cnt_inc(®);
|
|
|
|
card->hw_iface.bus_write_4(card->hw,AFT_PORT_REG(card,AFT_LINE_CFG_REG),reg);
|
|
card->u.aft.lcfg_reg=reg;
|
|
wan_set_bit(chan->logic_ch_num,&card->u.aft.tdm_logic_ch_map);
|
|
}
|
|
|
|
/* FE chan config */
|
|
if (card->wandev.fe_iface.if_config){
|
|
card->wandev.fe_iface.if_config(
|
|
&card->fe,
|
|
chan->time_slot_map,
|
|
chan->common.usedby);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aft_analog_chan_dev_unconfig(sdla_t *card, void *chan_ptr)
|
|
{
|
|
private_area_t *chan = (private_area_t *)chan_ptr;
|
|
u32 dma_ram_reg,reg;
|
|
volatile int i;
|
|
|
|
/* FE chan unconfig */
|
|
if (card->wandev.fe_iface.if_unconfig){
|
|
card->wandev.fe_iface.if_unconfig(
|
|
&card->fe,
|
|
chan->time_slot_map,
|
|
chan->common.usedby);
|
|
}
|
|
|
|
/* Select an HDLC logic channel for configuration */
|
|
if (chan->logic_ch_num != -1){
|
|
|
|
dma_ram_reg=AFT_PORT_REG(card,AFT_DMA_CHAIN_RAM_BASE_REG);
|
|
dma_ram_reg+=(chan->logic_ch_num*4);
|
|
|
|
card->hw_iface.bus_read_4(card->hw, dma_ram_reg, ®);
|
|
|
|
aft_dmachain_set_fifo_base(®,0x1F);
|
|
aft_dmachain_set_fifo_size(®,0);
|
|
card->hw_iface.bus_write_4(card->hw, dma_ram_reg, reg);
|
|
|
|
|
|
aft_free_logical_channel_num(card,chan->logic_ch_num);
|
|
aft_free_fifo_baddr_and_size(card,chan);
|
|
|
|
for (i=0;i<card->u.aft.num_of_time_slots;i++){
|
|
if (wan_test_bit(i,&chan->time_slot_map)){
|
|
wan_clear_bit(i,&card->u.aft.time_slot_map);
|
|
}
|
|
}
|
|
|
|
if (chan->channelized_cfg && !chan->hdlc_eng){
|
|
card->hw_iface.bus_read_4(card->hw,
|
|
AFT_PORT_REG(card,AFT_LINE_CFG_REG),®);
|
|
aft_lcfg_tdmv_cnt_dec(®);
|
|
card->hw_iface.bus_write_4(card->hw,
|
|
AFT_PORT_REG(card,AFT_LINE_CFG_REG),reg);
|
|
wan_clear_bit(chan->logic_ch_num,&card->u.aft.tdm_logic_ch_map);
|
|
}
|
|
|
|
/* Do not clear the logi_ch_num here.
|
|
We will do it at the end of del_if_private() funciton */
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int a200_check_ec_security(sdla_t *card)
|
|
{
|
|
u32 cfg_reg;
|
|
|
|
card->hw_iface.bus_read_4(card->hw,AFT_CHIP_CFG_REG, &cfg_reg);
|
|
if (wan_test_bit(AFT_CHIPCFG_A200_EC_SECURITY_BIT,&cfg_reg)){
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
unsigned char aft_analog_read_cpld(sdla_t *card, unsigned short cpld_off)
|
|
{
|
|
u16 org_off;
|
|
u8 tmp;
|
|
|
|
if (card->hw_iface.fe_test_and_set_bit(card->hw,0)){
|
|
DEBUG_EVENT("%s: %s:%d: Critical Error: Re-entry in FE!\n",
|
|
card->devname, __FUNCTION__,__LINE__);
|
|
return 0x00;
|
|
}
|
|
|
|
cpld_off |= AFT4_BIT_DEV_ADDR_CPLD;
|
|
|
|
/*ALEX: Save the current address. */
|
|
card->hw_iface.bus_read_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
&org_off);
|
|
|
|
card->hw_iface.bus_write_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
cpld_off);
|
|
|
|
card->hw_iface.bus_read_1(card->hw,AFT_MCPU_INTERFACE, &tmp);
|
|
|
|
/*ALEX: Restore original address */
|
|
card->hw_iface.bus_write_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
org_off);
|
|
card->hw_iface.fe_clear_bit(card->hw,0);
|
|
return tmp;
|
|
}
|
|
|
|
int aft_analog_write_cpld(sdla_t *card, unsigned short off, u_int16_t data_in)
|
|
{
|
|
u16 org_off;
|
|
u8 data=(u8)data_in;
|
|
|
|
if (card->hw_iface.fe_test_and_set_bit(card->hw,0)){
|
|
DEBUG_EVENT("%s: %s:%d: Critical Error: Re-entry in FE!\n",
|
|
card->devname, __FUNCTION__,__LINE__);
|
|
return 0x00;
|
|
}
|
|
|
|
off |= AFT4_BIT_DEV_ADDR_CPLD;
|
|
|
|
/*ALEX: Save the current original address */
|
|
card->hw_iface.bus_read_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
&org_off);
|
|
|
|
/* This delay is required to avoid bridge optimization
|
|
* (combining two writes together)*/
|
|
WP_DELAY(5);
|
|
|
|
card->hw_iface.bus_write_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
off);
|
|
|
|
/* This delay is required to avoid bridge optimization
|
|
* (combining two writes together)*/
|
|
WP_DELAY(5);
|
|
|
|
card->hw_iface.bus_write_1(card->hw,
|
|
AFT_MCPU_INTERFACE,
|
|
(u8)data);
|
|
/*ALEX: Restore the original address */
|
|
card->hw_iface.bus_write_2(card->hw,
|
|
AFT_MCPU_INTERFACE_ADDR,
|
|
org_off);
|
|
card->hw_iface.fe_clear_bit(card->hw,0);
|
|
return 0;
|
|
}
|
|
|
|
void aft_analog_fifo_adjust(sdla_t *card,u32 level)
|
|
{
|
|
return;
|
|
}
|
|
|
|
#if defined(CONFIG_WANPIPE_HWEC)
|
|
static int aft_analog_hwec_reset(void *pcard, int reset)
|
|
{
|
|
sdla_t *card = (sdla_t*)pcard;
|
|
wan_smp_flag_t smp_flags,flags;
|
|
int err = -EINVAL;
|
|
|
|
card->hw_iface.hw_lock(card->hw,&smp_flags);
|
|
wan_spin_lock_irq(&card->wandev.lock,&flags);
|
|
if (!reset){
|
|
DEBUG_EVENT("%s: Clear Echo Canceller chip reset.\n",
|
|
card->devname);
|
|
|
|
aft_analog_write_cpld(card, 0x00, 0x01);
|
|
WP_DELAY(1000);
|
|
err = 0;
|
|
|
|
}else{
|
|
DEBUG_EVENT("%s: Set Echo Canceller chip reset.\n",
|
|
card->devname);
|
|
aft_analog_write_cpld(card, 0x00, 0x00);
|
|
err = 0;
|
|
}
|
|
wan_spin_unlock_irq(&card->wandev.lock,&flags);
|
|
card->hw_iface.hw_unlock(card->hw,&smp_flags);
|
|
|
|
return err;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_WANPIPE_HWEC)
|
|
/******************************************************************************
|
|
** aft_analog_hwec_enable()
|
|
**
|
|
** Return: 0 - success
|
|
** 1 - channel out of channel map
|
|
** < 0 - failed
|
|
******************************************************************************/
|
|
#define AFT_REMORA_MUX_TS_EC_ENABLE 0x210
|
|
static int aft_analog_hwec_enable(void *pcard, int enable, int fe_chan)
|
|
{
|
|
sdla_t *card = (sdla_t*)pcard;
|
|
unsigned int value = 0x00;
|
|
int hw_chan = fe_chan-1;
|
|
|
|
WAN_ASSERT(card == NULL);
|
|
|
|
card->hw_iface.bus_read_4(
|
|
card->hw,
|
|
AFT_REMORA_MUX_TS_EC_ENABLE,
|
|
&value);
|
|
if (enable){
|
|
value |= (1 << hw_chan);
|
|
} else {
|
|
value &= ~(1 << fe_chan);
|
|
}
|
|
DEBUG_HWEC("[HWEC]: %s: %s bypass mode for fe_chan:%d (value=%X)...!\n",
|
|
card->devname,
|
|
(enable) ? "Enable" : "Disable",
|
|
fe_chan, value);
|
|
card->hw_iface.bus_write_4(
|
|
card->hw,
|
|
AFT_REMORA_MUX_TS_EC_ENABLE,
|
|
value);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
|
|
|