/* * top.v * * vim: ts=4 sw=4 * * Top-level for the icE1usb production boards * * Copyright (C) 2019-2020 Sylvain Munaut * SPDX-License-Identifier: CERN-OHL-S-2.0 */ `default_nettype none // `define WITH_SINGLE_CHANNEL // `define WITH_SB_I2C `define WITH_CUSTOM_I2C module top ( // E1 PHY input wire e1A_rx_hi_p, // input wire e1A_rx_hi_n, input wire e1A_rx_lo_p, // input wire e1A_rx_lo_n, output wire e1A_tx_hi, output wire e1A_tx_lo, input wire e1B_rx_hi_p, // input wire e1B_rx_hi_n, input wire e1B_rx_lo_p, // input wire e1B_rx_lo_n, output wire e1B_tx_hi, output wire e1B_tx_lo, output wire [1:0] e1_rx_bias, // USB inout wire usb_dp, inout wire usb_dn, output wire usb_pu, // Flash inout wire flash_mosi, inout wire flash_miso, inout wire flash_clk, inout wire flash_cs_n, // LED Shift register + Button input inout wire e1_led_rclk, // GPS output wire gps_reset_n, input wire gps_rx, output wire gps_tx, input wire gps_pps, // I2C inout wire i2c_sda, inout wire i2c_scl, // GPIOs inout wire [2:0] gpio, // Clock (30.72 MHz) input wire clk_in, output wire clk_tune_hi, output wire clk_tune_lo, // Debug UART input wire dbg_rx, output wire dbg_tx, // RGB LEDs output wire [2:0] rgb ); localparam integer WB_N = 4; genvar i; // Signals // ------- // Flash SPI internal signals wire flash_mosi_i, flash_miso_i, flash_clk_i; wire flash_mosi_o, flash_miso_o, flash_clk_o; wire flash_mosi_oe, flash_miso_oe, flash_clk_oe; wire flash_csn_o; // Peripheral wishbone wire [15:0] wb_addr; wire [31:0] wb_rdata [0:WB_N-1]; wire [31:0] wb_wdata; wire [ 3:0] wb_wmsk; wire wb_we; wire [WB_N-1:0] wb_cyc; wire [WB_N-1:0] wb_ack; wire [(WB_N*32)-1:0] wb_rdata_flat; // Ticks wire [1:0] tick_e1_rx; wire [1:0] tick_e1_tx; wire tick_usb_sof; // I2C wire i2c_scl_oe; wire i2c_scl_i; wire i2c_sda_oe; wire i2c_sda_i; // Aux UART wire aux_uart_tx; wire aux_uart_rx; // Led & Button wire [7:0] e1_led_state; wire e1_led_run; wire e1_led_active; wire spi_req; wire spi_gnt; wire [7:0] sr_val; wire sr_go; wire sr_rdy; wire btn_val; wire btn_stb; // Clocks / Reset wire rst_req; wire clk_sys; wire rst_sys; wire clk_48m; wire rst_48m; // SoC base // -------- // Instance soc_base #( .WB_N(WB_N), .E1_N(2), `ifdef WITH_SINGLE_CHANNEL .E1_UNIT_HAS_RX(2'b01), .E1_UNIT_HAS_TX(2'b01), `else .E1_UNIT_HAS_RX(2'b11), .E1_UNIT_HAS_TX(2'b11), `endif .E1_LIU(0) ) soc_I ( .e1_rx_hi_p ({e1B_rx_hi_p, e1A_rx_hi_p}), // .e1_rx_hi_n ({e1B_rx_hi_n, e1A_rx_hi_n}), .e1_rx_lo_p ({e1B_rx_lo_p, e1A_rx_lo_p}), // .e1_rx_lo_n ({e1B_rx_lo_n, e1A_rx_lo_n}), .e1_tx_hi ({e1B_tx_hi, e1A_tx_hi }), .e1_tx_lo ({e1B_tx_lo, e1A_tx_lo }), .e1_rx_data (), .e1_rx_clk (), .e1_tx_data (), .e1_tx_clk (), .usb_dp (usb_dp), .usb_dn (usb_dn), .usb_pu (usb_pu), .flash_mosi_i (flash_mosi_i), .flash_mosi_o (flash_mosi_o), .flash_mosi_oe(flash_mosi_oe), .flash_miso_i (flash_miso_i), .flash_miso_o (flash_miso_o), .flash_miso_oe(flash_miso_oe), .flash_clk_i (flash_clk_i), .flash_clk_o (flash_clk_o), .flash_clk_oe (flash_clk_oe), .flash_csn_o (flash_csn_o), .dbg_rx (dbg_rx), .dbg_tx (dbg_tx), .rgb (rgb), .wb_m_addr (wb_addr), .wb_m_rdata (wb_rdata_flat), .wb_m_wdata (wb_wdata), .wb_m_wmsk (wb_wmsk), .wb_m_we (wb_we), .wb_m_cyc (wb_cyc), .wb_m_ack (wb_ack), .tick_e1_rx (tick_e1_rx), .tick_e1_tx (tick_e1_tx), .tick_usb_sof (tick_usb_sof), .clk_sys (clk_sys), .rst_sys (rst_sys), .clk_48m (clk_48m), .rst_48m (rst_48m) ); // WB read data flattening for (i=0; i