gateware: no_rw_check fixes to cope with new yosys BRAM inferrence
Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Change-Id: Ic27dc22112f6603982126d447689dbe2202039c4
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@ -21,6 +21,7 @@ module soc_bram #(
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input wire clk
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);
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(* no_rw_check *)
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reg [31:0] mem [0:(1<<AW)-1];
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initial
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@ -1 +1 @@
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Subproject commit f9d1d47620ce81e9545287c585a5e8f0873b1661
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Subproject commit 59350da954e78424117ed01c55b5c7a12e524397
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