135 lines
3.8 KiB
C
135 lines
3.8 KiB
C
/* $Id$
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*
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* PCI2PI Pci Bridge support for xhfc_su.c
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*
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* Authors : Martin Bachem, Joerg Ciesielski
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* Contact : info@colognechip.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include "xhfc_su.h"
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#include "xhfc_pci2pi.h"
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static PCI2PI_cfg PCI2PI_config = {
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/* default PI_INTELMX config */
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.del_cs = 0,
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.del_rd = 0,
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.del_wr = 0,
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.del_ale = 0,
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.del_adr = 0,
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.del_dout = 0,
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.default_adr = 0x00,
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.default_dout = 0x00,
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.pi_mode = PI_MODE,
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.setup = 1,
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.hold = 1,
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.cycle = 1,
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.ale_adr_first = 0,
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.ale_adr_setup = 0,
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.ale_adr_hold = 1,
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.ale_adr_wait = 0,
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.pause_seq = 1,
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.pause_end = 0,
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.gpio_out = 0,
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.status_int_enable = 1,
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.pi_int_pol = 0,
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.pi_wait_enable = 0,
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.spi_cfg0 = 0,
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.spi_cfg1 = 0,
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.spi_cfg2 = 0,
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.spi_cfg3 = 0,
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.eep_recover = 4,
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};
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/***********************************/
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/* initialise the XHFC PCI Bridge */
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/* return 0 on success. */
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/***********************************/
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int
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init_pci_bridge(xhfc_hw * hw)
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{
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int err = -ENODEV;
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printk(KERN_INFO "%s %s: using PCI2PI Bridge at 0x%p\n",
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hw->card_name, __FUNCTION__, hw->hw_membase);
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/* test if Bridge regsiter accessable */
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WritePCI2PI_u32(hw, PCI2PI_DEL_CS, 0x0);
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if (ReadPCI2PI_u32(hw, PCI2PI_DEL_CS) == 0x00) {
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WritePCI2PI_u32(hw, PCI2PI_DEL_CS, 0xFFFFFFFF);
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if (ReadPCI2PI_u32(hw, PCI2PI_DEL_CS) == 0xF) {
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err = 0;
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}
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}
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if (err)
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return (err);
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/* enable hardware reset XHFC */
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WritePCI2PI_u32(hw, PCI2PI_GPIO_OUT, GPIO_OUT_VAL);
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WritePCI2PI_u32(hw, PCI2PI_PI_MODE, PCI2PI_config.pi_mode);
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WritePCI2PI_u32(hw, PCI2PI_DEL_CS, PCI2PI_config.del_cs);
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WritePCI2PI_u32(hw, PCI2PI_DEL_RD, PCI2PI_config.del_rd);
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WritePCI2PI_u32(hw, PCI2PI_DEL_WR, PCI2PI_config.del_wr);
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WritePCI2PI_u32(hw, PCI2PI_DEL_ALE, PCI2PI_config.del_ale);
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WritePCI2PI_u32(hw, PCI2PI_DEL_ADR, PCI2PI_config.del_adr);
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WritePCI2PI_u32(hw, PCI2PI_DEL_DOUT, PCI2PI_config.del_dout);
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WritePCI2PI_u32(hw, PCI2PI_DEFAULT_ADR, PCI2PI_config.default_adr);
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WritePCI2PI_u32(hw, PCI2PI_DEFAULT_DOUT,
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PCI2PI_config.default_dout);
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WritePCI2PI_u32(hw, PCI2PI_CYCLE_SHD, 0x80 * PCI2PI_config.setup
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+ 0x40 * PCI2PI_config.hold + PCI2PI_config.cycle);
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WritePCI2PI_u32(hw, PCI2PI_ALE_ADR_WHSF,
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PCI2PI_config.ale_adr_first +
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PCI2PI_config.ale_adr_setup * 2 +
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PCI2PI_config.ale_adr_hold * 4 +
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PCI2PI_config.ale_adr_wait * 8);
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WritePCI2PI_u32(hw, PCI2PI_CYCLE_PAUSE,
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0x10 * PCI2PI_config.pause_seq +
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PCI2PI_config.pause_end);
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WritePCI2PI_u32(hw, PCI2PI_STATUS_INT_ENABLE,
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PCI2PI_config.status_int_enable);
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WritePCI2PI_u32(hw, PCI2PI_PI_INT_POL,
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2 * PCI2PI_config.pi_wait_enable +
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PCI2PI_config.pi_int_pol);
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WritePCI2PI_u32(hw, PCI2PI_SPI_CFG0, PCI2PI_config.spi_cfg0);
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WritePCI2PI_u32(hw, PCI2PI_SPI_CFG1, PCI2PI_config.spi_cfg1);
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WritePCI2PI_u32(hw, PCI2PI_SPI_CFG2, PCI2PI_config.spi_cfg2);
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WritePCI2PI_u32(hw, PCI2PI_SPI_CFG3, PCI2PI_config.spi_cfg3);
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WritePCI2PI_u32(hw, PCI2PI_EEP_RECOVER, PCI2PI_config.eep_recover);
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ReadPCI2PI_u32(hw, PCI2PI_STATUS);
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/* release hardware reset XHFC */
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WritePCI2PI_u32(hw, PCI2PI_GPIO_OUT, GPIO_OUT_VAL | PCI2PI_GPIO7_NRST);
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udelay(10);
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return (err);
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}
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