210 lines
5.6 KiB
C
210 lines
5.6 KiB
C
/* $Id$
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*
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* mISDN driver for Colognechip xHFC chip
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*
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* Authors : Martin Bachem, Joerg Ciesielski
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* Contact : info@colognechip.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef _XHFC_SU_H_
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#define _XHFC_SU_H_
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#include <linux/timer.h>
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#include "channel.h"
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#include "bchannel.h"
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#include "xhfc24succ.h"
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#define DRIVER_NAME "XHFC"
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#ifndef CHIP_ID_2S4U
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#define CHIP_ID_2S4U 0x62
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#endif
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#ifndef CHIP_ID_4SU
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#define CHIP_ID_4SU 0x63
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#endif
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#ifndef CHIP_ID_1SU
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#define CHIP_ID_1SU 0x64
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#endif
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#ifndef CHIP_ID_2SU
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#define CHIP_ID_2SU 0x65
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#endif
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/* define bridge for chip register access */
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#define BRIDGE_UNKWOWN 0
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#define BRIDGE_PCI2PI 1 /* used at Cologne Chip AG's Evaluation Card */
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#define BRIDGE BRIDGE_PCI2PI
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#define MAX_PORT 4
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#define CHAN_PER_PORT 4 /* D, B1, B2, PCM */
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#define MAX_CHAN MAX_PORT * CHAN_PER_PORT
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/* flags in _u16 port mode */
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#define PORT_UNUSED 0x0000
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#define PORT_MODE_NT 0x0001
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#define PORT_MODE_TE 0x0002
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#define PORT_MODE_S0 0x0004
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#define PORT_MODE_UP 0x0008
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#define PORT_MODE_EXCH_POL 0x0010
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#define PORT_MODE_LOOP 0x0020
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#define NT_TIMER 0x8000
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/* NT / TE defines */
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#define NT_T1_COUNT 25 /* number of 4ms interrupts for G2 timeout */
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#define CLK_DLY_TE 0x0e /* CLKDEL in TE mode */
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#define CLK_DLY_NT 0x6c /* CLKDEL in NT mode */
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#define STA_ACTIVATE 0x60 /* start activation in A_SU_WR_STA */
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#define STA_DEACTIVATE 0x40 /* start deactivation in A_SU_WR_STA */
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#define LIF_MODE_NT 0x04 /* Line Interface NT mode */
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#define XHFC_TIMER_T3 8000 /* 8s activation timer T3 */
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#define XHFC_TIMER_T4 500 /* 500ms deactivation timer T4 */
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/* xhfc Layer1 physical commands */
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#define HFC_L1_ACTIVATE_TE 0x01
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#define HFC_L1_FORCE_DEACTIVATE_TE 0x02
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#define HFC_L1_ACTIVATE_NT 0x03
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#define HFC_L1_DEACTIVATE_NT 0x04
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#define HFC_L1_TESTLOOP_B1 0x05
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#define HFC_L1_TESTLOOP_B2 0x06
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/* xhfc Layer1 Flags (stored in xhfc_port_t->l1_flags) */
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#define HFC_L1_ACTIVATING 1
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#define HFC_L1_ACTIVATED 2
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#define HFC_L1_DEACTTIMER 3
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#define HFC_L1_ACTTIMER 4
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#define FIFO_MASK_TX 0x55555555
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#define FIFO_MASK_RX 0xAAAAAAAA
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/* DEBUG flags, use combined value for module parameter debug=x */
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#define DEBUG_HFC_INIT 0x0001
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#define DEBUG_HFC_MODE 0x0002
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#define DEBUG_HFC_S0_STATES 0x0004
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#define DEBUG_HFC_IRQ 0x0008
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#define DEBUG_HFC_FIFO_ERR 0x0010
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#define DEBUG_HFC_DTRACE 0x2000
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#define DEBUG_HFC_BTRACE 0x4000 /* very(!) heavy messageslog load */
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#define DEBUG_HFC_FIFO 0x8000 /* very(!) heavy messageslog load */
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#define USE_F0_COUNTER 1 /* akkumulate F0 counter diff every irq */
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/* private driver_data */
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typedef struct {
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int chip_id;
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char *device_name;
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} xhfc_param;
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/* channel struct for each fifo */
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typedef struct {
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bchannel_t *bch;
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channel_t *dch;
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int rx_idx; /* for D-channel */
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__u8 *rx_buf; /* for D-channel */
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int port; /* index pointer to port struct */
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} xhfc_chan_t;
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/* port struct for each S/U port */
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typedef struct {
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__u8 dpid; /* DChannel Protocoll ID */
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__u16 mode; /* NT/TE + ST/U */
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int nt_timer;
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u_long l1_flags;
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struct timer_list t3_timer; /* timer 3 for activation/deactivation */
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struct timer_list t4_timer; /* timer 4 for activation/deactivation */
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/* chip registers */
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reg_a_su_ctrl0 su_ctrl0;
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reg_a_su_ctrl1 su_ctrl1;
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reg_a_su_ctrl2 su_ctrl2;
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reg_a_su_ctrl3 su_ctrl3;
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} xhfc_port_t;
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struct _xhfx_hw;
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/**********************/
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/* hardware structure */
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/**********************/
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typedef struct _xhfx_hw {
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struct list_head list;
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spinlock_t lock;
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struct tasklet_struct tasklet; /* interrupt bottom half */
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int cardnum;
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__u8 param_idx; /* used to access module param arrays */
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int ifnum;
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__u8 testirq;
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int irq;
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int iobase;
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int nt_mode;
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u_char *membase;
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u_char *hw_membase;
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#if BRIDGE == BRIDGE_PCI2PI
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struct pci_dev *pdev;
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#endif
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xhfc_param driver_data;
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char card_name[60];
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int chip_id;
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int num_ports; /* number of S and U interfaces */
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int max_fifo; /* always 4 fifos per port */
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__u8 max_z; /* fifo depth -1 */
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xhfc_chan_t chan[MAX_CHAN]; /* line interfaces */
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xhfc_port_t port[MAX_PORT];
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__u32 irq_cnt; /* count irqs */
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__u32 f0_cnt; /* last F0 counter value */
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__u32 f0_akku; /* akkumulated f0 counter deltas */
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/* chip registers */
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reg_r_irq_ctrl irq_ctrl;
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reg_r_misc_irqmsk misc_irqmsk; /* mask of enabled interrupt sources */
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reg_r_misc_irq misc_irq; /* collect interrupt status bits */
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reg_r_su_irqmsk su_irqmsk; /* mask of line interface state change interrupts */
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reg_r_su_irq su_irq; /* collect interrupt status bits */
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reg_r_ti_wd ti_wd; /* timer interval */
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__u32 fifo_irq; /* fifo bl irq */
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__u32 fifo_irqmsk; /* fifo bl irq */
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} xhfc_hw;
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/* function prototypes */
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int setup_channel(xhfc_hw * hw, __u8 channel, int protocol);
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void xhfc_write_fifo(xhfc_hw * hw, __u8 channel);
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void xhfc_read_fifo(xhfc_hw * hw, __u8 channel);
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void print_fc(xhfc_hw * hw, __u8 fifo);
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void setup_fifo(xhfc_hw * hw, __u8 fifo, __u8 conhdlc, __u8 subcfg,
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__u8 fifoctrl, __u8 enable);
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void setup_su(xhfc_hw * hw, __u8 pt, __u8 bc, __u8 enable);
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#endif /* _XHFC_SU_H_ */
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