describe test loops enables by module param
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* <bit 4> 0x0010 Net side stack (NT mode)
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* <bit 5> 0x0020 Line Interface Mode (0=S0, 1=Up)
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* <bit 6> 0x0040 st line polarity (1=exchanged)
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* <bit 7> 0x0080 B1 channel loop
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* <bit 8> 0x0100 B2 channel loop
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* <bit 9> 0x0200 D channel loop
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* <bit 7> 0x0080 B1 channel loop ST-RX -> XHFC PCM -> ST-TX
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* <bit 8> 0x0100 B2 channel loop ST-RX -> XHFC PCM -> ST-TX
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* <bit 9> 0x0200 D channel loop ST-RX -> XHFC PCM -> ST-TX
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*
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* - layermask=<l1>[,l2,l3...] (32bit):
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* mask of layers to be used for D-channel stack
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