remove old files
This commit is contained in:
Karsten Keil
parent
33a9b1afac
commit
1a0b200bcb
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@ -1,861 +0,0 @@
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/* $Id$
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*
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* avm_pci.c low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
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* Thanks to AVM, Berlin for informations
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*
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* Author Karsten Keil (keil@isdn4linux.de)
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*
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* This file is (c) under GNU PUBLIC LICENSE
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*
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*/
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#define __NO_VERSION__
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#include <linux/config.h>
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#include "hisax.h"
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#include "isac.h"
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#include "isdnl1.h"
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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extern const char *CardType[];
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static const char *avm_pci_rev = "$Revision$";
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#define AVM_FRITZ_PCI 1
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#define AVM_FRITZ_PNP 2
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#ifndef PCI_VENDOR_ID_AVM
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#define PCI_VENDOR_ID_AVM 0x1244
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#endif
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#ifndef PCI_DEVICE_ID_AVM_FRITZ
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#define PCI_DEVICE_ID_AVM_FRITZ 0xa00
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#endif
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#define HDLC_FIFO 0x0
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#define HDLC_STATUS 0x4
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#define AVM_HDLC_1 0x00
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#define AVM_HDLC_2 0x01
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#define AVM_ISAC_FIFO 0x02
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#define AVM_ISAC_REG_LOW 0x04
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#define AVM_ISAC_REG_HIGH 0x06
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#define AVM_STATUS0_IRQ_ISAC 0x01
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#define AVM_STATUS0_IRQ_HDLC 0x02
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#define AVM_STATUS0_IRQ_TIMER 0x04
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#define AVM_STATUS0_IRQ_MASK 0x07
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#define AVM_STATUS0_RESET 0x01
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#define AVM_STATUS0_DIS_TIMER 0x02
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#define AVM_STATUS0_RES_TIMER 0x04
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#define AVM_STATUS0_ENA_IRQ 0x08
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#define AVM_STATUS0_TESTBIT 0x10
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#define AVM_STATUS1_INT_SEL 0x0f
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#define AVM_STATUS1_ENA_IOM 0x80
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#define HDLC_MODE_ITF_FLG 0x01
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#define HDLC_MODE_TRANS 0x02
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#define HDLC_MODE_CCR_7 0x04
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#define HDLC_MODE_CCR_16 0x08
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#define HDLC_MODE_TESTLOOP 0x80
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#define HDLC_INT_XPR 0x80
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#define HDLC_INT_XDU 0x40
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#define HDLC_INT_RPR 0x20
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#define HDLC_INT_MASK 0xE0
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#define HDLC_STAT_RME 0x01
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#define HDLC_STAT_RDO 0x10
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#define HDLC_STAT_CRCVFRRAB 0x0E
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#define HDLC_STAT_CRCVFR 0x06
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#define HDLC_STAT_RML_MASK 0x3f00
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#define HDLC_CMD_XRS 0x80
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#define HDLC_CMD_XME 0x01
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#define HDLC_CMD_RRS 0x20
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#define HDLC_CMD_XML_MASK 0x3f00
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/* Interface functions */
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static u_char
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ReadISAC(struct IsdnCardState *cs, u_char offset)
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{
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register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
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register u_char val;
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register long flags;
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save_flags(flags);
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cli();
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outb(idx, cs->hw.avm.cfg_reg + 4);
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val = inb(cs->hw.avm.isac + (offset & 0xf));
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restore_flags(flags);
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return (val);
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}
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static void
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WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
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register long flags;
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save_flags(flags);
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cli();
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outb(idx, cs->hw.avm.cfg_reg + 4);
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outb(value, cs->hw.avm.isac + (offset & 0xf));
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restore_flags(flags);
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}
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static void
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ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
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{
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outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
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insb(cs->hw.avm.isac, data, size);
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}
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static void
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WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
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{
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outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
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outsb(cs->hw.avm.isac, data, size);
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}
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static inline u_int
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ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
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{
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register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
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register u_int val;
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register long flags;
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save_flags(flags);
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cli();
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outl(idx, cs->hw.avm.cfg_reg + 4);
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val = inl(cs->hw.avm.isac + offset);
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restore_flags(flags);
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return (val);
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}
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static inline void
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WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
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{
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register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
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register long flags;
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save_flags(flags);
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cli();
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outl(idx, cs->hw.avm.cfg_reg + 4);
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outl(value, cs->hw.avm.isac + offset);
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restore_flags(flags);
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}
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static inline u_char
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ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
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{
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register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
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register u_char val;
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register long flags;
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save_flags(flags);
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cli();
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outb(idx, cs->hw.avm.cfg_reg + 4);
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val = inb(cs->hw.avm.isac + offset);
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restore_flags(flags);
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return (val);
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}
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static inline void
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WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
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{
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register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
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register long flags;
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save_flags(flags);
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cli();
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outb(idx, cs->hw.avm.cfg_reg + 4);
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outb(value, cs->hw.avm.isac + offset);
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restore_flags(flags);
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}
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static u_char
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ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
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{
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return(0xff & ReadHDLCPCI(cs, chan, offset));
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}
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static void
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WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
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{
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WriteHDLCPCI(cs, chan, offset, value);
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}
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static inline
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struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
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{
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if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
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return(&cs->bcs[0]);
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else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
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return(&cs->bcs[1]);
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else
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return(NULL);
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}
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void inline
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hdlc_sched_event(struct BCState *bcs, int event)
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{
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bcs->event |= 1 << event;
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queue_task(&bcs->tqueue, &tq_immediate);
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mark_bh(IMMEDIATE_BH);
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}
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void
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write_ctrl(struct BCState *bcs, int which) {
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if (bcs->cs->debug & L1_DEB_HSCX)
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debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
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'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
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if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
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WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
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} else {
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if (which & 4)
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WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
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bcs->hw.hdlc.ctrl.sr.mode);
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if (which & 2)
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WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
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bcs->hw.hdlc.ctrl.sr.xml);
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if (which & 1)
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WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
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bcs->hw.hdlc.ctrl.sr.cmd);
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}
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}
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void
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modehdlc(struct BCState *bcs, int mode, int bc)
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{
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struct IsdnCardState *cs = bcs->cs;
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int hdlc = bcs->channel;
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
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'A' + hdlc, bcs->mode, mode, hdlc, bc);
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bcs->hw.hdlc.ctrl.ctrl = 0;
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switch (mode) {
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case (-1): /* used for init */
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bcs->mode = 1;
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bcs->channel = bc;
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bc = 0;
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case (L1_MODE_NULL):
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if (bcs->mode == L1_MODE_NULL)
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return;
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bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
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bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
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write_ctrl(bcs, 5);
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bcs->mode = L1_MODE_NULL;
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bcs->channel = bc;
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break;
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case (L1_MODE_TRANS):
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bcs->mode = mode;
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bcs->channel = bc;
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bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
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bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
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write_ctrl(bcs, 5);
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bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
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write_ctrl(bcs, 1);
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bcs->hw.hdlc.ctrl.sr.cmd = 0;
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hdlc_sched_event(bcs, B_XMTBUFREADY);
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break;
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case (L1_MODE_HDLC):
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bcs->mode = mode;
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bcs->channel = bc;
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bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
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bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
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write_ctrl(bcs, 5);
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bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
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write_ctrl(bcs, 1);
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bcs->hw.hdlc.ctrl.sr.cmd = 0;
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hdlc_sched_event(bcs, B_XMTBUFREADY);
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break;
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}
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}
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static inline void
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hdlc_empty_fifo(struct BCState *bcs, int count)
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{
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register u_int *ptr;
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u_char *p;
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u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
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int cnt=0;
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struct IsdnCardState *cs = bcs->cs;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hdlc_empty_fifo %d", count);
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if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
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return;
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}
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ptr = (u_int *) p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
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bcs->hw.hdlc.rcvidx += count;
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if (cs->subtyp == AVM_FRITZ_PCI) {
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outl(idx, cs->hw.avm.cfg_reg + 4);
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while (cnt < count) {
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#ifdef __powerpc__
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#ifdef CONFIG_APUS
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*ptr++ = in_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
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#else
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*ptr++ = in_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
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#endif /* CONFIG_APUS */
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#else
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*ptr++ = inl(cs->hw.avm.isac);
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#endif /* __powerpc__ */
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cnt += 4;
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}
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} else {
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outb(idx, cs->hw.avm.cfg_reg + 4);
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while (cnt < count) {
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*p++ = inb(cs->hw.avm.isac);
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cnt++;
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}
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}
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if (cs->debug & L1_DEB_HSCX_FIFO) {
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char *t = bcs->blog;
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if (cs->subtyp == AVM_FRITZ_PNP)
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p = (u_char *) ptr;
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t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
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bcs->channel ? 'B' : 'A', count);
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QuickHex(t, p, count);
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debugl1(cs, bcs->blog);
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}
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}
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static inline void
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hdlc_fill_fifo(struct BCState *bcs)
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{
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struct IsdnCardState *cs = bcs->cs;
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int count, cnt =0;
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int fifo_size = 32;
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u_char *p;
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u_int *ptr;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hdlc_fill_fifo");
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if (!bcs->tx_skb)
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return;
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if (bcs->tx_skb->len <= 0)
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return;
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bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
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if (bcs->tx_skb->len > fifo_size) {
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count = fifo_size;
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} else {
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count = bcs->tx_skb->len;
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if (bcs->mode != L1_MODE_TRANS)
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bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
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}
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hdlc_fill_fifo %d/%ld", count, bcs->tx_skb->len);
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ptr = (u_int *) p = bcs->tx_skb->data;
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skb_pull(bcs->tx_skb, count);
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bcs->tx_cnt -= count;
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bcs->hw.hdlc.count += count;
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bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
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write_ctrl(bcs, 3); /* sets the correct index too */
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if (cs->subtyp == AVM_FRITZ_PCI) {
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while (cnt<count) {
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#ifdef __powerpc__
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#ifdef CONFIG_APUS
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out_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
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#else
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out_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
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#endif /* CONFIG_APUS */
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#else
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outl(*ptr++, cs->hw.avm.isac);
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#endif /* __powerpc__ */
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cnt += 4;
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}
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} else {
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while (cnt<count) {
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outb(*p++, cs->hw.avm.isac);
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cnt++;
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}
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}
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if (cs->debug & L1_DEB_HSCX_FIFO) {
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char *t = bcs->blog;
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if (cs->subtyp == AVM_FRITZ_PNP)
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p = (u_char *) ptr;
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t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
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bcs->channel ? 'B' : 'A', count);
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QuickHex(t, p, count);
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debugl1(cs, bcs->blog);
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}
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}
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static void
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fill_hdlc(struct BCState *bcs)
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{
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long flags;
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save_flags(flags);
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cli();
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hdlc_fill_fifo(bcs);
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restore_flags(flags);
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}
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static inline void
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HDLC_irq(struct BCState *bcs, u_int stat) {
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int len;
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struct sk_buff *skb;
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if (bcs->cs->debug & L1_DEB_HSCX)
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debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
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if (stat & HDLC_INT_RPR) {
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if (stat & HDLC_STAT_RDO) {
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if (bcs->cs->debug & L1_DEB_HSCX)
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debugl1(bcs->cs, "RDO");
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else
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debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
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bcs->hw.hdlc.ctrl.sr.xml = 0;
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bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
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write_ctrl(bcs, 1);
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bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
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write_ctrl(bcs, 1);
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bcs->hw.hdlc.rcvidx = 0;
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} else {
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if (!(len = (stat & HDLC_STAT_RML_MASK)>>8))
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len = 32;
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hdlc_empty_fifo(bcs, len);
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if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
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if (((stat & HDLC_STAT_CRCVFRRAB)==HDLC_STAT_CRCVFR) ||
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(bcs->mode == L1_MODE_TRANS)) {
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if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
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printk(KERN_WARNING "HDLC: receive out of memory\n");
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else {
|
||||
memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
|
||||
bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
|
||||
skb_queue_tail(&bcs->rqueue, skb);
|
||||
}
|
||||
bcs->hw.hdlc.rcvidx = 0;
|
||||
hdlc_sched_event(bcs, B_RCVBUFREADY);
|
||||
} else {
|
||||
if (bcs->cs->debug & L1_DEB_HSCX)
|
||||
debugl1(bcs->cs, "invalid frame");
|
||||
else
|
||||
debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
|
||||
bcs->hw.hdlc.rcvidx = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (stat & HDLC_INT_XDU) {
|
||||
/* Here we lost an TX interrupt, so
|
||||
* restart transmitting the whole frame.
|
||||
*/
|
||||
if (bcs->tx_skb) {
|
||||
skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
|
||||
bcs->tx_cnt += bcs->hw.hdlc.count;
|
||||
bcs->hw.hdlc.count = 0;
|
||||
// hdlc_sched_event(bcs, B_XMTBUFREADY);
|
||||
if (bcs->cs->debug & L1_DEB_WARN)
|
||||
debugl1(bcs->cs, "ch%d XDU", bcs->channel);
|
||||
} else if (bcs->cs->debug & L1_DEB_WARN)
|
||||
debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
|
||||
bcs->hw.hdlc.ctrl.sr.xml = 0;
|
||||
bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
|
||||
write_ctrl(bcs, 1);
|
||||
bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
|
||||
write_ctrl(bcs, 1);
|
||||
hdlc_fill_fifo(bcs);
|
||||
} else if (stat & HDLC_INT_XPR) {
|
||||
if (bcs->tx_skb) {
|
||||
if (bcs->tx_skb->len) {
|
||||
hdlc_fill_fifo(bcs);
|
||||
return;
|
||||
} else {
|
||||
if (bcs->st->lli.l1writewakeup &&
|
||||
(PACKET_NOACK != bcs->tx_skb->pkt_type))
|
||||
bcs->st->lli.l1writewakeup(bcs->st, bcs->hw.hdlc.count);
|
||||
dev_kfree_skb(bcs->tx_skb);
|
||||
bcs->hw.hdlc.count = 0;
|
||||
bcs->tx_skb = NULL;
|
||||
}
|
||||
}
|
||||
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
||||
bcs->hw.hdlc.count = 0;
|
||||
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
||||
hdlc_fill_fifo(bcs);
|
||||
} else {
|
||||
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||||
hdlc_sched_event(bcs, B_XMTBUFREADY);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline void
|
||||
HDLC_irq_main(struct IsdnCardState *cs)
|
||||
{
|
||||
u_int stat;
|
||||
long flags;
|
||||
struct BCState *bcs;
|
||||
|
||||
save_flags(flags);
|
||||
cli();
|
||||
if (cs->subtyp == AVM_FRITZ_PCI) {
|
||||
stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
|
||||
} else {
|
||||
stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
|
||||
if (stat & HDLC_INT_RPR)
|
||||
stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS+1))<<8;
|
||||
}
|
||||
if (stat & HDLC_INT_MASK) {
|
||||
if (!(bcs = Sel_BCS(cs, 0))) {
|
||||
if (cs->debug)
|
||||
debugl1(cs, "hdlc spurious channel 0 IRQ");
|
||||
} else
|
||||
HDLC_irq(bcs, stat);
|
||||
}
|
||||
if (cs->subtyp == AVM_FRITZ_PCI) {
|
||||
stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
|
||||
} else {
|
||||
stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
|
||||
if (stat & HDLC_INT_RPR)
|
||||
stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS+1))<<8;
|
||||
}
|
||||
if (stat & HDLC_INT_MASK) {
|
||||
if (!(bcs = Sel_BCS(cs, 1))) {
|
||||
if (cs->debug)
|
||||
debugl1(cs, "hdlc spurious channel 1 IRQ");
|
||||
} else
|
||||
HDLC_irq(bcs, stat);
|
||||
}
|
||||
restore_flags(flags);
|
||||
}
|
||||
|
||||
void
|
||||
hdlc_l2l1(struct PStack *st, int pr, void *arg)
|
||||
{
|
||||
struct sk_buff *skb = arg;
|
||||
long flags;
|
||||
|
||||
switch (pr) {
|
||||
case (PH_DATA | REQUEST):
|
||||
save_flags(flags);
|
||||
cli();
|
||||
if (st->l1.bcs->tx_skb) {
|
||||
skb_queue_tail(&st->l1.bcs->squeue, skb);
|
||||
restore_flags(flags);
|
||||
} else {
|
||||
st->l1.bcs->tx_skb = skb;
|
||||
test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
||||
st->l1.bcs->hw.hdlc.count = 0;
|
||||
restore_flags(flags);
|
||||
st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
|
||||
}
|
||||
break;
|
||||
case (PH_PULL | INDICATION):
|
||||
if (st->l1.bcs->tx_skb) {
|
||||
printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
|
||||
break;
|
||||
}
|
||||
test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
||||
st->l1.bcs->tx_skb = skb;
|
||||
st->l1.bcs->hw.hdlc.count = 0;
|
||||
st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
|
||||
break;
|
||||
case (PH_PULL | REQUEST):
|
||||
if (!st->l1.bcs->tx_skb) {
|
||||
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
||||
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
||||
} else
|
||||
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
||||
break;
|
||||
case (PH_ACTIVATE | REQUEST):
|
||||
test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
|
||||
modehdlc(st->l1.bcs, st->l1.mode, st->l1.bc);
|
||||
l1_msg_b(st, pr, arg);
|
||||
break;
|
||||
case (PH_DEACTIVATE | REQUEST):
|
||||
l1_msg_b(st, pr, arg);
|
||||
break;
|
||||
case (PH_DEACTIVATE | CONFIRM):
|
||||
test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
|
||||
test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
||||
modehdlc(st->l1.bcs, 0, st->l1.bc);
|
||||
st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
close_hdlcstate(struct BCState *bcs)
|
||||
{
|
||||
modehdlc(bcs, 0, 0);
|
||||
if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
|
||||
if (bcs->hw.hdlc.rcvbuf) {
|
||||
kfree(bcs->hw.hdlc.rcvbuf);
|
||||
bcs->hw.hdlc.rcvbuf = NULL;
|
||||
}
|
||||
if (bcs->blog) {
|
||||
kfree(bcs->blog);
|
||||
bcs->blog = NULL;
|
||||
}
|
||||
discard_queue(&bcs->rqueue);
|
||||
discard_queue(&bcs->squeue);
|
||||
if (bcs->tx_skb) {
|
||||
dev_kfree_skb(bcs->tx_skb);
|
||||
bcs->tx_skb = NULL;
|
||||
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
|
||||
{
|
||||
if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
|
||||
if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
|
||||
printk(KERN_WARNING
|
||||
"HiSax: No memory for hdlc.rcvbuf\n");
|
||||
return (1);
|
||||
}
|
||||
if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
|
||||
printk(KERN_WARNING
|
||||
"HiSax: No memory for bcs->blog\n");
|
||||
test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
|
||||
kfree(bcs->hw.hdlc.rcvbuf);
|
||||
bcs->hw.hdlc.rcvbuf = NULL;
|
||||
return (2);
|
||||
}
|
||||
skb_queue_head_init(&bcs->rqueue);
|
||||
skb_queue_head_init(&bcs->squeue);
|
||||
}
|
||||
bcs->tx_skb = NULL;
|
||||
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||||
bcs->event = 0;
|
||||
bcs->hw.hdlc.rcvidx = 0;
|
||||
bcs->tx_cnt = 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
setstack_hdlc(struct PStack *st, struct BCState *bcs)
|
||||
{
|
||||
bcs->channel = st->l1.bc;
|
||||
if (open_hdlcstate(st->l1.hardware, bcs))
|
||||
return (-1);
|
||||
st->l1.bcs = bcs;
|
||||
st->l2.l2l1 = hdlc_l2l1;
|
||||
setstack_manager(st);
|
||||
bcs->st = st;
|
||||
setstack_l1_B(st);
|
||||
return (0);
|
||||
}
|
||||
|
||||
HISAX_INITFUNC(void
|
||||
clear_pending_hdlc_ints(struct IsdnCardState *cs))
|
||||
{
|
||||
u_int val;
|
||||
|
||||
if (cs->subtyp == AVM_FRITZ_PCI) {
|
||||
val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
|
||||
debugl1(cs, "HDLC 1 STA %x", val);
|
||||
val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
|
||||
debugl1(cs, "HDLC 2 STA %x", val);
|
||||
} else {
|
||||
val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
|
||||
debugl1(cs, "HDLC 1 STA %x", val);
|
||||
val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
|
||||
debugl1(cs, "HDLC 1 RML %x", val);
|
||||
val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
|
||||
debugl1(cs, "HDLC 1 MODE %x", val);
|
||||
val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
|
||||
debugl1(cs, "HDLC 1 VIN %x", val);
|
||||
val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
|
||||
debugl1(cs, "HDLC 2 STA %x", val);
|
||||
val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
|
||||
debugl1(cs, "HDLC 2 RML %x", val);
|
||||
val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
|
||||
debugl1(cs, "HDLC 2 MODE %x", val);
|
||||
val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
|
||||
debugl1(cs, "HDLC 2 VIN %x", val);
|
||||
}
|
||||
}
|
||||
|
||||
HISAX_INITFUNC(void
|
||||
inithdlc(struct IsdnCardState *cs))
|
||||
{
|
||||
cs->bcs[0].BC_SetStack = setstack_hdlc;
|
||||
cs->bcs[1].BC_SetStack = setstack_hdlc;
|
||||
cs->bcs[0].BC_Close = close_hdlcstate;
|
||||
cs->bcs[1].BC_Close = close_hdlcstate;
|
||||
modehdlc(cs->bcs, -1, 0);
|
||||
modehdlc(cs->bcs + 1, -1, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
avm_pcipnp_interrupt(int intno, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
struct IsdnCardState *cs = dev_id;
|
||||
u_char val;
|
||||
u_char sval;
|
||||
|
||||
if (!cs) {
|
||||
printk(KERN_WARNING "AVM PCI: Spurious interrupt!\n");
|
||||
return;
|
||||
}
|
||||
sval = inb(cs->hw.avm.cfg_reg + 2);
|
||||
if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK)
|
||||
/* possible a shared IRQ reqest */
|
||||
return;
|
||||
if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
|
||||
val = ReadISAC(cs, ISAC_ISTA);
|
||||
isac_interrupt(cs, val);
|
||||
}
|
||||
if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
|
||||
HDLC_irq_main(cs);
|
||||
}
|
||||
WriteISAC(cs, ISAC_MASK, 0xFF);
|
||||
WriteISAC(cs, ISAC_MASK, 0x0);
|
||||
}
|
||||
|
||||
static void
|
||||
reset_avmpcipnp(struct IsdnCardState *cs)
|
||||
{
|
||||
long flags;
|
||||
|
||||
printk(KERN_INFO "AVM PCI/PnP: reset\n");
|
||||
save_flags(flags);
|
||||
sti();
|
||||
outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
|
||||
current->state = TASK_UNINTERRUPTIBLE;
|
||||
schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
|
||||
outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
|
||||
outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
|
||||
current->state = TASK_UNINTERRUPTIBLE;
|
||||
schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
|
||||
printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
|
||||
}
|
||||
|
||||
static int
|
||||
AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
|
||||
{
|
||||
switch (mt) {
|
||||
case CARD_RESET:
|
||||
reset_avmpcipnp(cs);
|
||||
return(0);
|
||||
case CARD_RELEASE:
|
||||
outb(0, cs->hw.avm.cfg_reg + 2);
|
||||
release_region(cs->hw.avm.cfg_reg, 32);
|
||||
return(0);
|
||||
case CARD_INIT:
|
||||
clear_pending_isac_ints(cs);
|
||||
initisac(cs);
|
||||
clear_pending_hdlc_ints(cs);
|
||||
inithdlc(cs);
|
||||
outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
|
||||
cs->hw.avm.cfg_reg + 2);
|
||||
WriteISAC(cs, ISAC_MASK, 0);
|
||||
outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
|
||||
AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
|
||||
/* RESET Receiver and Transmitter */
|
||||
WriteISAC(cs, ISAC_CMDR, 0x41);
|
||||
return(0);
|
||||
case CARD_TEST:
|
||||
return(0);
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
|
||||
static struct pci_dev *dev_avm __initdata = NULL;
|
||||
|
||||
__initfunc(int
|
||||
setup_avm_pcipnp(struct IsdnCard *card))
|
||||
{
|
||||
u_int val, ver;
|
||||
struct IsdnCardState *cs = card->cs;
|
||||
char tmp[64];
|
||||
|
||||
strcpy(tmp, avm_pci_rev);
|
||||
printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
|
||||
if (cs->typ != ISDN_CTYPE_FRITZPCI)
|
||||
return (0);
|
||||
if (card->para[1]) {
|
||||
cs->hw.avm.cfg_reg = card->para[1];
|
||||
cs->irq = card->para[0];
|
||||
cs->subtyp = AVM_FRITZ_PNP;
|
||||
} else {
|
||||
#if CONFIG_PCI
|
||||
if (!pci_present()) {
|
||||
printk(KERN_ERR "FritzPCI: no PCI bus present\n");
|
||||
return(0);
|
||||
}
|
||||
if ((dev_avm = pci_find_device(PCI_VENDOR_ID_AVM,
|
||||
PCI_DEVICE_ID_AVM_FRITZ, dev_avm))) {
|
||||
cs->irq = dev_avm->irq;
|
||||
if (!cs->irq) {
|
||||
printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
|
||||
return(0);
|
||||
}
|
||||
if (pci_enable_device(dev_avm))
|
||||
return(0);
|
||||
cs->hw.avm.cfg_reg = dev_avm->base_address[ 1] & PCI_BASE_ADDRESS_IO_MASK;
|
||||
if (!cs->hw.avm.cfg_reg) {
|
||||
printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
|
||||
return(0);
|
||||
}
|
||||
cs->subtyp = AVM_FRITZ_PCI;
|
||||
} else {
|
||||
printk(KERN_WARNING "FritzPCI: No PCI card found\n");
|
||||
return(0);
|
||||
}
|
||||
cs->irq_flags |= SA_SHIRQ;
|
||||
#else
|
||||
printk(KERN_WARNING "FritzPCI: NO_PCI_BIOS\n");
|
||||
return (0);
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
|
||||
if (check_region((cs->hw.avm.cfg_reg), 32)) {
|
||||
printk(KERN_WARNING
|
||||
"HiSax: %s config port %x-%x already in use\n",
|
||||
CardType[card->typ],
|
||||
cs->hw.avm.cfg_reg,
|
||||
cs->hw.avm.cfg_reg + 31);
|
||||
return (0);
|
||||
} else {
|
||||
request_region(cs->hw.avm.cfg_reg, 32,
|
||||
(cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP");
|
||||
}
|
||||
switch (cs->subtyp) {
|
||||
case AVM_FRITZ_PCI:
|
||||
val = inl(cs->hw.avm.cfg_reg);
|
||||
printk(KERN_INFO "AVM PCI: stat %#x\n", val);
|
||||
printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
|
||||
val & 0xff, (val>>8) & 0xff);
|
||||
cs->BC_Read_Reg = &ReadHDLC_s;
|
||||
cs->BC_Write_Reg = &WriteHDLC_s;
|
||||
break;
|
||||
case AVM_FRITZ_PNP:
|
||||
val = inb(cs->hw.avm.cfg_reg);
|
||||
ver = inb(cs->hw.avm.cfg_reg + 1);
|
||||
printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
|
||||
reset_avmpcipnp(cs);
|
||||
cs->BC_Read_Reg = &ReadHDLCPnP;
|
||||
cs->BC_Write_Reg = &WriteHDLCPnP;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
|
||||
return(0);
|
||||
}
|
||||
printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
|
||||
(cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
|
||||
cs->irq, cs->hw.avm.cfg_reg);
|
||||
|
||||
cs->readisac = &ReadISAC;
|
||||
cs->writeisac = &WriteISAC;
|
||||
cs->readisacfifo = &ReadISACfifo;
|
||||
cs->writeisacfifo = &WriteISACfifo;
|
||||
cs->BC_Send_Data = &fill_hdlc;
|
||||
cs->cardmsg = &AVM_card_msg;
|
||||
cs->irq_func = &avm_pcipnp_interrupt;
|
||||
ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
|
||||
return (1);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,465 +0,0 @@
|
|||
/* $Id$
|
||||
*
|
||||
* Basic declarations, defines and prototypes
|
||||
*
|
||||
* This file is (c) under GNU PUBLIC LICENSE
|
||||
*
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/major.h>
|
||||
#include <asm/segment.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/malloc.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/isdnif.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/hisaxif.h>
|
||||
#include "helper.h"
|
||||
|
||||
#define CARD_RESET 0x00F0
|
||||
#define CARD_INIT 0x00F2
|
||||
#define CARD_RELEASE 0x00F3
|
||||
#define CARD_TEST 0x00F4
|
||||
#define CARD_AUX_IND 0x00F5
|
||||
|
||||
#define PH_TESTLOOP 0x0140
|
||||
#define PH_PAUSE 0x0150
|
||||
|
||||
#define DL_FLUSH 0x0224
|
||||
#define MDL_INFO_SETUP 0x02E0
|
||||
#define MDL_INFO_CONN 0x02E4
|
||||
#define MDL_INFO_REL 0x02E8
|
||||
|
||||
#define CC_SETUP 0x0300
|
||||
#define CC_RESUME 0x0304
|
||||
#define CC_MORE_INFO 0x0310
|
||||
#define CC_IGNORE 0x0320
|
||||
#define CC_REJECT 0x0324
|
||||
#define CC_SETUP_COMPL 0x0330
|
||||
#define CC_PROCEEDING 0x0340
|
||||
#define CC_ALERTING 0x0344
|
||||
#define CC_PROGRESS 0x0348
|
||||
#define CC_CONNECT 0x0350
|
||||
#define CC_CHARGE 0x0354
|
||||
#define CC_NOTIFY 0x0358
|
||||
#define CC_DISCONNECT 0x0360
|
||||
#define CC_RELEASE 0x0368
|
||||
#define CC_SUSPEND 0x0370
|
||||
#define CC_PROCEED_SEND 0x0374
|
||||
#define CC_REDIR 0x0378
|
||||
#define CC_T302 0x0382
|
||||
#define CC_T303 0x0383
|
||||
#define CC_T304 0x0384
|
||||
#define CC_T305 0x0385
|
||||
#define CC_T308_1 0x0388
|
||||
#define CC_T308_2 0x038A
|
||||
#define CC_T309 0x0309
|
||||
#define CC_T310 0x0390
|
||||
#define CC_T313 0x0393
|
||||
#define CC_T318 0x0398
|
||||
#define CC_T319 0x0399
|
||||
#define CC_TSPID 0x03A0
|
||||
#define CC_NOSETUP_RSP 0x03E0
|
||||
#define CC_SETUP_ERR 0x03E1
|
||||
#define CC_SUSPEND_ERR 0x03E2
|
||||
#define CC_RESUME_ERR 0x03E3
|
||||
#define CC_CONNECT_ERR 0x03E4
|
||||
#define CC_RELEASE_ERR 0x03E5
|
||||
#define CC_RESTART 0x03F4
|
||||
#define CC_TDSS1_IO 0x13F4 /* DSS1 IO user timer */
|
||||
#define CC_TNI1_IO 0x13F5 /* NI1 IO user timer */
|
||||
|
||||
/* define maximum number of possible waiting incoming calls */
|
||||
#define MAX_WAITING_CALLS 2
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define MAX_DFRAME_LEN 260
|
||||
#define MAX_DFRAME_LEN_L1 300
|
||||
#define HSCX_BUFMAX 4096
|
||||
#define MAX_DATA_SIZE (HSCX_BUFMAX - 4)
|
||||
#define MAX_DATA_MEM (HSCX_BUFMAX + 64)
|
||||
#define RAW_BUFMAX (((HSCX_BUFMAX*6)/5) + 5)
|
||||
#define MAX_HEADER_LEN 4
|
||||
#define MAX_WINDOW 8
|
||||
#define MAX_MON_FRAME 32
|
||||
#define MAX_DLOG_SPACE 2048
|
||||
#define MAX_BLOG_SPACE 256
|
||||
|
||||
/* #define I4L_IRQ_FLAG SA_INTERRUPT */
|
||||
#define I4L_IRQ_FLAG 0
|
||||
|
||||
/*
|
||||
* Statemachine
|
||||
*/
|
||||
|
||||
struct FsmInst;
|
||||
|
||||
typedef void (* FSMFNPTR)(struct FsmInst *, int, void *);
|
||||
|
||||
struct Fsm {
|
||||
FSMFNPTR *jumpmatrix;
|
||||
int state_count, event_count;
|
||||
char **strEvent, **strState;
|
||||
};
|
||||
|
||||
struct FsmInst {
|
||||
struct Fsm *fsm;
|
||||
int state;
|
||||
int debug;
|
||||
void *userdata;
|
||||
int userint;
|
||||
void (*printdebug) (struct FsmInst *, char *, ...);
|
||||
};
|
||||
|
||||
struct FsmNode {
|
||||
int state, event;
|
||||
void (*routine) (struct FsmInst *, int, void *);
|
||||
};
|
||||
|
||||
struct FsmTimer {
|
||||
struct FsmInst *fi;
|
||||
struct timer_list tl;
|
||||
int event;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
#define FLG_L1_ACTIVATING 1
|
||||
#define FLG_L1_ACTIVATED 2
|
||||
#define FLG_L1_DEACTTIMER 3
|
||||
#define FLG_L1_ACTTIMER 4
|
||||
#define FLG_L1_T3RUN 5
|
||||
#define FLG_L1_PULL_REQ 6
|
||||
#define FLG_L1_UINT 7
|
||||
|
||||
#define PACKET_NOACK 250
|
||||
|
||||
struct hdlc_stat_reg {
|
||||
#ifdef __BIG_ENDIAN
|
||||
u_char fill __attribute__((packed));
|
||||
u_char mode __attribute__((packed));
|
||||
u_char xml __attribute__((packed));
|
||||
u_char cmd __attribute__((packed));
|
||||
#else
|
||||
u_char cmd __attribute__((packed));
|
||||
u_char xml __attribute__((packed));
|
||||
u_char mode __attribute__((packed));
|
||||
u_char fill __attribute__((packed));
|
||||
#endif
|
||||
};
|
||||
|
||||
struct isar_reg {
|
||||
unsigned int Flags;
|
||||
volatile u_char bstat;
|
||||
volatile u_char iis;
|
||||
volatile u_char cmsb;
|
||||
volatile u_char clsb;
|
||||
volatile u_char par[8];
|
||||
};
|
||||
|
||||
struct isar_hw {
|
||||
int dpath;
|
||||
int txcnt;
|
||||
int mml;
|
||||
u_char state;
|
||||
u_char cmd;
|
||||
u_char mod;
|
||||
u_char newcmd;
|
||||
u_char newmod;
|
||||
char try_mod;
|
||||
struct timer_list ftimer;
|
||||
u_char conmsg[16];
|
||||
struct isar_reg *reg;
|
||||
};
|
||||
|
||||
struct hdlc_hw {
|
||||
union {
|
||||
u_int ctrl;
|
||||
struct hdlc_stat_reg sr;
|
||||
} ctrl;
|
||||
u_int stat;
|
||||
int count; /* Current skb sent count */
|
||||
};
|
||||
|
||||
|
||||
#define BC_FLG_INIT 1
|
||||
#define BC_FLG_ACTIV 2
|
||||
#define BC_FLG_BUSY 3
|
||||
#define BC_FLG_NOFRAME 4
|
||||
#define BC_FLG_HALF 5
|
||||
#define BC_FLG_EMPTY 6
|
||||
#define BC_FLG_ORIG 7
|
||||
#define BC_FLG_DLEETX 8
|
||||
#define BC_FLG_LASTDLE 9
|
||||
#define BC_FLG_FIRST 10
|
||||
#define BC_FLG_LASTDATA 11
|
||||
#define BC_FLG_NMD_DATA 12
|
||||
#define BC_FLG_FTI_RUN 13
|
||||
#define BC_FLG_LL_OK 14
|
||||
#define BC_FLG_LL_CONN 15
|
||||
|
||||
typedef struct _bchannel_t {
|
||||
int channel;
|
||||
int protocol;
|
||||
int Flag;
|
||||
int debug;
|
||||
hisaxinstance_t inst;
|
||||
u_char (*BC_Read_Reg)(void *, int, u_char);
|
||||
void (*BC_Write_Reg)(void *, int, u_char, u_char);
|
||||
struct sk_buff *next_skb;
|
||||
u_int next_nr;
|
||||
u_char *tx_buf;
|
||||
int tx_idx;
|
||||
int tx_len;
|
||||
u_char *rx_buf;
|
||||
int rx_idx;
|
||||
struct sk_buff_head rqueue; /* B-Channel receive Queue */
|
||||
u_char *blog;
|
||||
u_char *conmsg;
|
||||
struct timer_list transbusy;
|
||||
struct tq_struct tqueue;
|
||||
int event;
|
||||
int err_crc;
|
||||
int err_tx;
|
||||
int err_rdo;
|
||||
int err_inv;
|
||||
union {
|
||||
struct hdlc_hw hdlc;
|
||||
struct isar_hw isar;
|
||||
} hw;
|
||||
} bchannel_t;
|
||||
|
||||
struct avm_hw {
|
||||
unsigned int cfg_reg;
|
||||
unsigned int isac;
|
||||
unsigned int hscx[2];
|
||||
unsigned int isacfifo;
|
||||
unsigned int hscxfifo[2];
|
||||
unsigned int counter;
|
||||
};
|
||||
|
||||
struct sedl_hw {
|
||||
unsigned int cfg_reg;
|
||||
unsigned int adr;
|
||||
unsigned int isac;
|
||||
unsigned int hscx;
|
||||
unsigned int reset_on;
|
||||
unsigned int reset_off;
|
||||
struct isar_reg isar;
|
||||
unsigned int chip;
|
||||
unsigned int bus;
|
||||
};
|
||||
|
||||
struct arcofi_msg {
|
||||
struct arcofi_msg *next;
|
||||
u_char receive;
|
||||
u_char len;
|
||||
u_char msg[10];
|
||||
};
|
||||
|
||||
struct isac_chip {
|
||||
int ph_state;
|
||||
u_char *mon_tx;
|
||||
u_char *mon_rx;
|
||||
int mon_txp;
|
||||
int mon_txc;
|
||||
int mon_rxp;
|
||||
struct arcofi_msg *arcofi_list;
|
||||
struct timer_list arcofitimer;
|
||||
struct wait_queue *arcofi_wait;
|
||||
u_char arcofi_bc;
|
||||
u_char arcofi_state;
|
||||
u_char mocr;
|
||||
u_char adf2;
|
||||
};
|
||||
|
||||
#define HW_IOM1 0
|
||||
#define HW_IPAC 1
|
||||
#define HW_ISAR 2
|
||||
#define HW_ARCOFI 3
|
||||
#define FLG_TWO_DCHAN 4
|
||||
#define FLG_TX_BUSY 5
|
||||
#define FLG_TX_NEXT 6
|
||||
#define FLG_L1_DBUSY 7
|
||||
#define FLG_DBUSY_TIMER 8
|
||||
#define FLG_LOCK_ATOMIC 9
|
||||
#define FLG_ARCOFI_TIMER 10
|
||||
#define FLG_ARCOFI_ERROR 11
|
||||
#define FLG_HW_L1_UINT 12
|
||||
#define FLG_HW_INIT 13
|
||||
|
||||
typedef struct _dchannel_t {
|
||||
hisaxinstance_t inst;
|
||||
u_int DFlags;
|
||||
u_char (*readisac) (void *, u_char);
|
||||
void (*writeisac) (void *, u_char, u_char);
|
||||
void (*readisacfifo) (void *, u_char *, int);
|
||||
void (*writeisacfifo) (void *, u_char *, int);
|
||||
char *dlog;
|
||||
int debug;
|
||||
u_int reqnr;
|
||||
u_char *rx_buf;
|
||||
int rx_idx;
|
||||
struct sk_buff *next_skb;
|
||||
u_int next_nr;
|
||||
u_char *tx_buf;
|
||||
int tx_idx;
|
||||
int tx_len;
|
||||
int event;
|
||||
int err_crc;
|
||||
int err_tx;
|
||||
int err_rx;
|
||||
union {
|
||||
struct isac_chip isac;
|
||||
} hw;
|
||||
struct sk_buff_head rqueue; /* D-channel receive queue */
|
||||
struct tq_struct tqueue;
|
||||
struct timer_list dbusytimer;
|
||||
} dchannel_t;
|
||||
|
||||
#define MON0_RX 1
|
||||
#define MON1_RX 2
|
||||
#define MON0_TX 4
|
||||
#define MON1_TX 8
|
||||
|
||||
#define HISAX_MAX_CARDS 8
|
||||
|
||||
#define ISDN_CTYPE_16_0 1
|
||||
#define ISDN_CTYPE_8_0 2
|
||||
#define ISDN_CTYPE_16_3 3
|
||||
#define ISDN_CTYPE_PNP 4
|
||||
#define ISDN_CTYPE_A1 5
|
||||
#define ISDN_CTYPE_ELSA 6
|
||||
#define ISDN_CTYPE_ELSA_PNP 7
|
||||
#define ISDN_CTYPE_TELESPCMCIA 8
|
||||
#define ISDN_CTYPE_IX1MICROR2 9
|
||||
#define ISDN_CTYPE_ELSA_PCMCIA 10
|
||||
#define ISDN_CTYPE_DIEHLDIVA 11
|
||||
#define ISDN_CTYPE_ASUSCOM 12
|
||||
#define ISDN_CTYPE_TELEINT 13
|
||||
#define ISDN_CTYPE_TELES3C 14
|
||||
#define ISDN_CTYPE_SEDLBAUER 15
|
||||
#define ISDN_CTYPE_SPORTSTER 16
|
||||
#define ISDN_CTYPE_MIC 17
|
||||
#define ISDN_CTYPE_ELSA_PCI 18
|
||||
#define ISDN_CTYPE_COMPAQ_ISA 19
|
||||
#define ISDN_CTYPE_NETJET_S 20
|
||||
#define ISDN_CTYPE_TELESPCI 21
|
||||
#define ISDN_CTYPE_SEDLBAUER_PCMCIA 22
|
||||
#define ISDN_CTYPE_AMD7930 23
|
||||
#define ISDN_CTYPE_NICCY 24
|
||||
#define ISDN_CTYPE_S0BOX 25
|
||||
#define ISDN_CTYPE_A1_PCMCIA 26
|
||||
#define ISDN_CTYPE_FRITZPCI 27
|
||||
#define ISDN_CTYPE_SEDLBAUER_FAX 28
|
||||
#define ISDN_CTYPE_ISURF 29
|
||||
#define ISDN_CTYPE_ACERP10 30
|
||||
#define ISDN_CTYPE_HSTSAPHIR 31
|
||||
#define ISDN_CTYPE_BKM_A4T 32
|
||||
#define ISDN_CTYPE_SCT_QUADRO 33
|
||||
#define ISDN_CTYPE_GAZEL 34
|
||||
#define ISDN_CTYPE_HFC_PCI 35
|
||||
#define ISDN_CTYPE_W6692 36
|
||||
#define ISDN_CTYPE_HFC_SX 37
|
||||
#define ISDN_CTYPE_NETJET_U 38
|
||||
#define ISDN_CTYPE_HFC_SP_PCMCIA 39
|
||||
#define ISDN_CTYPE_COUNT 39
|
||||
|
||||
|
||||
#ifdef ISDN_CHIP_ISAC
|
||||
#undef ISDN_CHIP_ISAC
|
||||
#endif
|
||||
|
||||
#ifndef __initfunc
|
||||
#define __initfunc(__arginit) __arginit
|
||||
#endif
|
||||
|
||||
#ifndef __initdata
|
||||
#define __initdata
|
||||
#endif
|
||||
|
||||
#define HISAX_INITFUNC(__arginit) __initfunc(__arginit)
|
||||
#define HISAX_INITDATA __initdata
|
||||
|
||||
#ifdef CONFIG_HISAX_FRITZPCI
|
||||
#define CARD_FRITZPCI 1
|
||||
#ifndef ISDN_CHIP_ISAC
|
||||
#define ISDN_CHIP_ISAC 1
|
||||
#endif
|
||||
#else
|
||||
#define CARD_FRITZPCI 0
|
||||
#endif
|
||||
|
||||
#define TEI_PER_CARD 1
|
||||
|
||||
/* L1 Debug */
|
||||
#define L1_DEB_WARN 0x01
|
||||
#define L1_DEB_INTSTAT 0x02
|
||||
#define L1_DEB_ISAC 0x04
|
||||
#define L1_DEB_ISAC_FIFO 0x08
|
||||
#define L1_DEB_HSCX 0x10
|
||||
#define L1_DEB_HSCX_FIFO 0x20
|
||||
#define L1_DEB_LAPD 0x40
|
||||
#define L1_DEB_IPAC 0x80
|
||||
#define L1_DEB_RECEIVE_FRAME 0x100
|
||||
#define L1_DEB_MONITOR 0x200
|
||||
#define DEB_DLOG_HEX 0x400
|
||||
#define DEB_DLOG_VERBOSE 0x800
|
||||
|
||||
struct IsdnCard {
|
||||
int typ;
|
||||
int protocol; /* EDSS1, 1TR6 or NI1 */
|
||||
unsigned int para[4];
|
||||
void *card;
|
||||
};
|
||||
|
||||
int init_dchannel(dchannel_t *);
|
||||
int free_dchannel(dchannel_t *);
|
||||
int init_bchannel(bchannel_t *);
|
||||
int free_bchannel(bchannel_t *);
|
||||
void FsmNew(struct Fsm *fsm, struct FsmNode *fnlist, int fncount);
|
||||
void FsmFree(struct Fsm *fsm);
|
||||
int FsmEvent(struct FsmInst *fi, int event, void *arg);
|
||||
void FsmChangeState(struct FsmInst *fi, int newstate);
|
||||
void FsmInitTimer(struct FsmInst *fi, struct FsmTimer *ft);
|
||||
int FsmAddTimer(struct FsmTimer *ft, int millisec, int event,
|
||||
void *arg, int where);
|
||||
void FsmRestartTimer(struct FsmTimer *ft, int millisec, int event,
|
||||
void *arg, int where);
|
||||
void FsmDelTimer(struct FsmTimer *ft, int where);
|
||||
int jiftime(char *s, long mark);
|
||||
|
||||
int QuickHex(char *txt, u_char * p, int cnt);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#define HZDELAY(jiffs) {int tout = jiffs; while (tout--) udelay(1000000/HZ);}
|
||||
|
||||
char *HiSax_getrev(const char *revision);
|
||||
#ifdef __powerpc__
|
||||
#include <linux/pci.h>
|
||||
static inline int pci_enable_device(struct pci_dev *dev)
|
||||
{
|
||||
u16 cmd;
|
||||
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
||||
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_SERR;
|
||||
cmd &= ~PCI_COMMAND_FAST_BACK;
|
||||
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
||||
return(0);
|
||||
}
|
||||
#else
|
||||
#define pci_enable_device(dev) !dev
|
||||
#endif /* __powerpc__ */
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
/* $Id$
|
||||
*
|
||||
* Layer 1 defines
|
||||
*
|
||||
* This file is (c) under GNU PUBLIC LICENSE
|
||||
*
|
||||
*/
|
||||
|
||||
#define D_RCVBUFREADY 0
|
||||
#define D_XMTBUFREADY 1
|
||||
#define D_L1STATECHANGE 2
|
||||
#define D_CLEARBUSY 3
|
||||
#define D_RX_MON0 4
|
||||
#define D_RX_MON1 5
|
||||
#define D_TX_MON0 6
|
||||
#define D_TX_MON1 7
|
||||
|
||||
#define B_RCVBUFREADY 0
|
||||
#define B_XMTBUFREADY 1
|
||||
|
||||
Loading…
Reference in New Issue