189 lines
6.2 KiB
C
189 lines
6.2 KiB
C
/* $Id$
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*
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* ISDN low-level module for Eicon active ISDN-Cards (PCI part).
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*
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* Copyright 1998-2000 by Armin Schindler (mac@melware.de)
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* Copyright 1999,2000 Cytronics & Melware (info@melware.de)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* $Log$
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* Revision 1.3 1999/03/29 11:19:51 armin
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* I/O stuff now in seperate file (eicon_io.c)
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* Old ISA type cards (S,SX,SCOM,Quadro,S2M) implemented.
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*
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* Revision 1.2 1999/03/02 12:37:50 armin
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* Added some important checks.
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* Analog Modem with DSP.
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* Channels will be added to Link-Level after loading firmware.
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*
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* Revision 1.1 1999/01/01 18:09:46 armin
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* First checkin of new eicon driver.
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* DIVA-Server BRI/PCI and PRI/PCI are supported.
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* Old diehl code is obsolete.
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*
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*
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*/
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#ifndef eicon_pci_h
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#define eicon_pci_h
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#ifdef __KERNEL__
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#define PCI_VENDOR_EICON 0x1133
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#define PCI_DIVA_PRO20 0xe001 /* Not supported */
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#define PCI_DIVA20 0xe002 /* Not supported */
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#define PCI_DIVA_PRO20_U 0xe003 /* Not supported */
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#define PCI_DIVA20_U 0xe004 /* Not supported */
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#define PCI_MAESTRA 0xe010
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#define PCI_MAESTRAQ 0xe012
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#define PCI_MAESTRAQ_U 0xe013
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#define PCI_MAESTRAP 0xe014
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#define DIVA_PRO20 1
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#define DIVA20 2
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#define DIVA_PRO20_U 3
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#define DIVA20_U 4
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#define MAESTRA 5
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#define MAESTRAQ 6
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#define MAESTRAQ_U 7
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#define MAESTRAP 8
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#define TRUE 1
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#define FALSE 0
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#define DIVAS_SIGNATURE 0x4447
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/* MAESTRA BRI PCI */
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#define M_RESET 0x10 /* offset of reset register */
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#define M_DATA 0x00 /* offset of data register */
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#define M_ADDR 0x04 /* offset of address register */
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#define M_ADDRH 0x0c /* offset of high address register */
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#define M_DSP_CODE_LEN 0xbf7d0000
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#define M_DSP_CODE 0xbf7d0004 /* max 128K DSP-Code */
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#define M_DSP_CODE_BASE 0xbf7a0000
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#define M_MAX_DSP_CODE_SIZE 0x00050000 /* max 320K DSP-Code (Telindus) */
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/* MAESTRA PRI PCI */
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#define MP_SHARED_RAM_OFFSET 0x1000 /* offset of shared RAM base in the DRAM memory bar */
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#define MP_IRQ_RESET 0xc18 /* offset of interrupt status register in the CONFIG memory bar */
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#define MP_IRQ_RESET_VAL 0xfe /* value to clear an interrupt */
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#define MP_PROTOCOL_ADDR 0xa0011000 /* load address of protocol code */
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#define MP_DSP_ADDR 0xa03c0000 /* load address of DSP code */
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#define MP_MAX_PROTOCOL_CODE_SIZE 0x000a0000 /* max 640K Protocol-Code */
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#define MP_DSP_CODE_BASE 0xa03a0000
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#define MP_MAX_DSP_CODE_SIZE 0x00060000 /* max 384K DSP-Code */
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#define MP_RESET 0x20 /* offset of RESET register in the DEVICES memory bar */
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/* RESET register bits */
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#define _MP_S2M_RESET 0x10 /* active lo */
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#define _MP_LED2 0x08 /* 1 = on */
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#define _MP_LED1 0x04 /* 1 = on */
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#define _MP_DSP_RESET 0x02 /* active lo */
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#define _MP_RISC_RESET 0x81 /* active hi, bit 7 for compatibility with old boards */
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/* boot interface structure */
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typedef struct {
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__u32 cmd __attribute__ ((packed));
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__u32 addr __attribute__ ((packed));
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__u32 len __attribute__ ((packed));
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__u32 err __attribute__ ((packed));
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__u32 live __attribute__ ((packed));
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__u32 reserved[(0x1020>>2)-6] __attribute__ ((packed));
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__u32 signature __attribute__ ((packed));
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__u8 data[1]; /* real interface description */
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} eicon_pci_boot;
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#define DL_PARA_IO_TYPE 0
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#define DL_PARA_MEM_TYPE 1
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typedef struct tag_dsp_download_space
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{
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__u16 type; /* see definitions above to differ union elements */
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union
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{
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struct
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{
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__u32 r3addr;
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__u16 ioADDR;
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__u16 ioADDRH;
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__u16 ioDATA;
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__u16 BadData; /* in case of verify error */
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__u16 GoodData;
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} io; /* for io based adapters */
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struct
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{
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__u32 r3addr;
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eicon_pci_boot *boot;
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__u32 BadData; /* in case of verify error */
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__u32 GoodData;
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__u16 timeout;
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} mem; /* for memory based adapters */
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} dat;
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} t_dsp_download_space;
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/* Shared memory */
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typedef union {
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eicon_pci_boot boot;
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} eicon_pci_shmem;
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/*
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* card's description
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*/
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typedef struct {
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int ramsize;
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int irq; /* IRQ */
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unsigned int PCIram;
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unsigned int PCIreg;
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unsigned int PCIcfg;
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long int serial; /* Serial No. */
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int channels; /* No. of supported channels */
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void* card;
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eicon_pci_shmem* shmem; /* Shared-memory area */
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unsigned char* intack; /* Int-Acknowledge */
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unsigned char* stopcpu; /* Writing here stops CPU */
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unsigned char* startcpu; /* Writing here starts CPU */
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unsigned char type; /* card type */
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unsigned char irqprobe; /* Flag: IRQ-probing */
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unsigned char mvalid; /* Flag: Memory is valid */
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unsigned char ivalid; /* Flag: IRQ is valid */
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unsigned char master; /* Flag: Card is Quadro 1/4 */
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void* generic; /* Ptr to generic card struct */
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} eicon_pci_card;
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extern int eicon_pci_load_pri(eicon_pci_card *card, eicon_pci_codebuf *cb);
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extern int eicon_pci_load_bri(eicon_pci_card *card, eicon_pci_codebuf *cb);
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extern void eicon_pci_release(eicon_pci_card *card);
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extern void eicon_pci_printpar(eicon_pci_card *card);
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extern int eicon_pci_find_card(char *ID);
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#endif /* __KERNEL__ */
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#endif /* eicon_pci_h */
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