129 lines
2.8 KiB
C
129 lines
2.8 KiB
C
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/* $Id$
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* specific defines for CCD's HFC 2BDS0
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*
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* Author Karsten Keil (keil@temic-ech.spacenet.de)
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*
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*
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* $Log$
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*
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*
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*/
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#define HFCD_CIRM 0x18
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#define HFCD_CTMT 0x19
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#define HFCD_INT_M1 0x1A
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#define HFCD_INT_M2 0x1B
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#define HFCD_INT_S1 0x1E
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#define HFCD_STAT 0x1C
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#define HFCD_STAT_DISB 0x1D
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#define HFCD_STATES 0x30
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#define HFCD_SCTRL 0x31
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#define HFCD_TEST 0x32
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#define HFCD_SQ 0x34
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#define HFCD_CLKDEL 0x37
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#define HFCD_MST_MODE 0x2E
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#define HFCD_CONN 0x2F
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#define HFCD_FIFO 0x80
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#define HFCD_Z1 0x10
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#define HFCD_Z2 0x18
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#define HFCD_Z_LOW 0x00
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#define HFCD_Z_HIGH 0x04
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#define HFCD_F1_INC 0x12
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#define HFCD_FIFO_IN 0x16
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#define HFCD_F1 0x1a
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#define HFCD_F2 0x1e
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#define HFCD_F2_INC 0x22
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#define HFCD_FIFO_OUT 0x26
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#define HFCD_REC 0x01
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#define HFCD_SEND 0x00
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#define HFCB_FIFO 0x80
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#define HFCB_Z1 0x00
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#define HFCB_Z2 0x08
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#define HFCB_Z_LOW 0x00
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#define HFCB_Z_HIGH 0x04
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#define HFCB_F1_INC 0x28
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#define HFCB_FIFO_IN 0x2c
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#define HFCB_F1 0x30
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#define HFCB_F2 0x34
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#define HFCB_F2_INC 0x38
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#define HFCB_FIFO_OUT 0x3c
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#define HFCB_REC 0x01
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#define HFCB_SEND 0x00
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#define HFCB_B1 0x00
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#define HFCB_B2 0x02
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#define HFCB_CHANNEL(ch) (ch ? HFCB_B2 : HFCB_B1)
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#define HFCD_STATUS 0
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#define HFCD_DATA 1
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#define HFCD_DATA_NODEB 2
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/* Status (READ) */
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#define HFCD_BUSY 0x01
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#define HFCD_BUSY_NBUSY 0x04
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#define HFCD_TIMER_ELAP 0x10
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#define HFCD_STATINT 0x20
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#define HFCD_FRAMEINT 0x40
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#define HFCD_ANYINT 0x80
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/* CTMT (Write) */
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#define HFCD_CLTIMER 0x80
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#define HFCD_TIM25 0x00
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#define HFCD_TIM50 0x08
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#define HFCD_TIM400 0x10
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#define HFCD_TIM800 0x18
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#define HFCD_AUTO_TIMER 0x20
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#define HFCD_TRANSB2 0x02
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#define HFCD_TRANSB1 0x01
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/* CIRM (Write) */
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#define HFCD_RESET 0x08
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#define HFCD_MEM8K 0x10
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#define HFCD_INTA 0x01
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#define HFCD_INTB 0x02
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#define HFCD_INTC 0x03
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#define HFCD_INTD 0x04
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#define HFCD_INTE 0x05
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#define HFCD_INTF 0x06
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/* INT_M1;INT_S1 */
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#define HFCD_INTS_B1TRANS 0x01
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#define HFCD_INTS_B2TRANS 0x02
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#define HFCD_INTS_DTRANS 0x04
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#define HFCD_INTS_B1REC 0x08
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#define HFCD_INTS_B2REC 0x10
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#define HFCD_INTS_DREC 0x20
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#define HFCD_INTS_L1STATE 0x40
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#define HFCD_INTS_TIMER 0x80
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/* INT_M2 */
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#define HFCD_IRQ_ENABLE 0x08
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/* STATES */
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#define HFCD_LOAD_STATE 0x10
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#define HFCD_ACTIVATE 0x20
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#define HFCD_DO_ACTION 0x40
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/* HFCD_MST_MODE */
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#define HFCD_MASTER 0x01
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/* HFCD_SCTRL */
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#define SCTRL_B1_ENA 0x01
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#define SCTRL_B2_ENA 0x02
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#define SCTRL_LOW_PRIO 0x08
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#define SCTRL_SQ_ENA 0x10
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#define SCTRL_TEST 0x20
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#define SCTRL_NONE_CAP 0x40
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#define SCTRL_PWR_DOWN 0x80
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/* HFCD_TEST */
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#define HFCD_AUTO_AWAKE 0x01
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extern void main_irq_2bds0(struct BCState *bcs);
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extern void init2bds0(struct IsdnCardState *cs);
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extern void release2bds0(struct IsdnCardState *cs);
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extern void hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val);
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extern void set_cs_func(struct IsdnCardState *cs);
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