forked from cellular-infrastructure/osmo-pcu
alloc: Load balancing for algo A
Currently only the first enabled PDCH will be used. Beside the throughput this will also limit the number of TBFs: - number of UL TBFs <= 7 - number of DL TBFs <= 32 This commit changes the allocation algorithm to use the PDCH with the least number of attached TBFs. This will improve the troughput in both directions and the UL limits: - number of UL TBFs <= min(32, N_PDCH * 7) UL TBFs Ticket: #1794 Sponsored-by: On-Waves ehf
This commit is contained in:
Jacob Erlbeck
parent
9380f5d218
commit
ec478756cc
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@ -26,6 +26,7 @@
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#include <gprs_ms.h>
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#include <errno.h>
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#include <values.h>
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/* 3GPP TS 05.02 Annex B.1 */
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@ -99,10 +100,13 @@ static inline int8_t find_free_usf(struct gprs_rlcmac_pdch *pdch)
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return -1;
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}
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static int find_enabled_pdch(struct gprs_rlcmac_trx *trx, const uint8_t start_ts)
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static int find_possible_pdchs(struct gprs_rlcmac_trx *trx,
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uint8_t mask, const char *mask_reason = NULL)
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{
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int ts;
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for (ts = start_ts; ts < 8; ts++) {
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unsigned ts;
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int valid_ts_set = 0;
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for (ts = 0; ts < ARRAY_SIZE(trx->pdch); ts++) {
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struct gprs_rlcmac_pdch *pdch;
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pdch = &trx->pdch[ts];
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@ -111,10 +115,75 @@ static int find_enabled_pdch(struct gprs_rlcmac_trx *trx, const uint8_t start_ts
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"not enabled\n", ts);
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continue;
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}
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return ts;
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if (((1 << ts) & mask) == 0) {
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if (mask_reason)
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LOGP(DRLCMAC, LOGL_DEBUG,
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"- Skipping TS %d, because %s\n",
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ts, mask_reason);
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continue;
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}
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valid_ts_set |= 1 << ts;
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}
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return 8;
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return valid_ts_set;
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}
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static int find_least_busy_pdch(struct gprs_rlcmac_trx *trx,
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enum gprs_rlcmac_tbf_direction dir,
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uint8_t mask,
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int *free_usf = 0)
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{
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unsigned ts;
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int min_used = INT_MAX;
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int min_ts = -1;
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int min_usf = -1;
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for (ts = 0; ts < ARRAY_SIZE(trx->pdch); ts++) {
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struct gprs_rlcmac_pdch *pdch = &trx->pdch[ts];
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int num_tbfs;
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int usf = -1; /* must be signed */
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if (((1 << ts) & mask) == 0)
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continue;
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num_tbfs = pdch->num_tbfs(dir);
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if (num_tbfs < min_used) {
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/* We have found a candidate */
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/* Make sure that an USF is available */
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if (dir == GPRS_RLCMAC_UL_TBF) {
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usf = find_free_usf(pdch);
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if (usf < 0) {
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LOGP(DRLCMAC, LOGL_DEBUG,
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"- Skipping TS %d, because "
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"no USF available\n", ts);
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continue;
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}
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}
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if (min_ts >= 0)
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LOGP(DRLCMAC, LOGL_DEBUG,
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"- Skipping TS %d, because "
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"num TBFs %d > %d\n",
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min_ts, min_used, num_tbfs);
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min_used = num_tbfs;
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min_ts = ts;
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min_usf = usf;
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} else {
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LOGP(DRLCMAC, LOGL_DEBUG,
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"- Skipping TS %d, because "
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"num TBFs %d >= %d\n",
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ts, num_tbfs, min_used);
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}
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}
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if (min_ts < 0)
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return -1;
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if (free_usf)
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*free_usf = min_usf;
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return min_ts;
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}
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static void attach_tbf_to_pdch(struct gprs_rlcmac_pdch *pdch,
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@ -154,29 +223,54 @@ int alloc_algorithm_a(struct gprs_rlcmac_bts *bts,
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struct gprs_rlcmac_tbf *tbf, uint32_t cust, uint8_t single)
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{
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struct gprs_rlcmac_pdch *pdch;
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uint8_t ts;
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int ts = -1;
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int usf = -1;
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int mask = 0xff;
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const char *mask_reason = NULL;
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struct gprs_rlcmac_tbf *ref_tbf;
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LOGP(DRLCMAC, LOGL_DEBUG, "Slot Allocation (Algorithm A) for class "
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"%d\n", tbf->ms_class());
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ts = find_enabled_pdch(tbf->trx, 0);
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if (ts == 8)
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if ((ref_tbf = ms->tbf(tbf->direction)))
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mask_reason = "need to reuse TS";
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else if ((ref_tbf = ms->tbf(reverse(tbf->direction))))
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mask_reason = ref_tbf->direction == GPRS_RLCMAC_UL_TBF ?
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"not an uplink TBF" : "not a downlink TBF";
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if (ref_tbf)
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ts = ref_tbf->first_common_ts;
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if (ts >= 0)
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mask = 1 << ts;
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mask = find_possible_pdchs(tbf->trx, mask, mask_reason);
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if (!mask)
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return -EINVAL;
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ts = find_least_busy_pdch(tbf->trx, tbf->direction, mask, &usf);
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if (ts < 0) {
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LOGP(DRLCMAC, LOGL_NOTICE, "- Failed "
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"to allocate a TS, no USF available\n");
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return -EBUSY;
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}
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pdch = &tbf->trx->pdch[ts];
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if (tbf->direction == GPRS_RLCMAC_UL_TBF) {
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int8_t usf; /* must be signed */
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struct gprs_rlcmac_ul_tbf *ul_tbf = static_cast<gprs_rlcmac_ul_tbf *>(tbf);
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/* if USF available */
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usf = find_free_usf(pdch);
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if (usf < 0)
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usf = find_free_usf(pdch);
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if (usf < 0) {
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LOGP(DRLCMAC, LOGL_NOTICE, "- Failed "
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"allocating TS=%d, no USF available\n", ts);
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return -EBUSY;
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}
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LOGP(DRLCMAC, LOGL_DEBUG, "- Assign uplink "
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"TS=%d USF=%d\n", ts, usf);
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LOGP(DRLCMAC, LOGL_DEBUG, "- Assign uplink TS=%d USF=%d\n",
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ts, usf);
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assign_uplink_tbf_usf(pdch, ul_tbf, usf);
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} else {
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struct gprs_rlcmac_dl_tbf *dl_tbf = static_cast<gprs_rlcmac_dl_tbf *>(tbf);
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@ -110,11 +110,11 @@ static void test_alloc_a()
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{
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/* slots 2 - 3 */
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test_alloc_a(GPRS_RLCMAC_DL_TBF, 0x0c, 32);
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test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x0c, 7);
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test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x0c, 14);
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/* slots 1 - 5 */
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test_alloc_a(GPRS_RLCMAC_DL_TBF, 0x1e, 32);
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test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x1e, 7);
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test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x1e, 28);
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}
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static void dump_assignment(struct gprs_rlcmac_tbf *tbf, const char *dir)
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@ -557,13 +557,13 @@ static void test_successive_allocation(algo_t algo, unsigned min_class,
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}
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printf(" Successfully allocated %d UL TBFs\n", counter);
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OSMO_ASSERT(counter >= expect_num);
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OSMO_ASSERT(counter == expect_num);
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}
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static void test_successive_allocation()
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{
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_AND_DL,
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7, "algorithm A (UL and DL)");
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32, "algorithm A (UL and DL)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_AND_DL,
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7, "algorithm B class 10 (UL and DL)");
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test_successive_allocation(alloc_algorithm_b, 12, 12, TEST_MODE_UL_AND_DL,
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@ -574,29 +574,29 @@ static void test_successive_allocation()
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18, "algorithm B class 1-29 (UL and DL)");
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_AND_UL,
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7, "algorithm A (DL and UL)");
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32, "algorithm A (DL and UL)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_AND_UL,
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7, "algorithm B class 10 (DL and UL)");
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_AFTER_UL,
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7, "algorithm A (DL after UL)");
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32, "algorithm A (DL after UL)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_AFTER_UL,
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7, "algorithm B class 10 (DL after UL)");
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32, "algorithm B class 10 (DL after UL)");
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_AFTER_DL,
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7, "algorithm A (UL after DL)");
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32, "algorithm A (UL after DL)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_AFTER_DL,
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7, "algorithm B class 10 (UL after DL)");
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_ONLY,
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7, "algorithm A (UL only)");
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32, "algorithm A (UL only)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_ONLY,
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7, "algorithm B class 10 (UL only)");
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test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_ONLY,
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7, "algorithm A (DL ONLY)");
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32, "algorithm A (DL ONLY)");
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test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_ONLY,
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7, "algorithm B class 10 (DL ONLY)");
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32, "algorithm B class 10 (DL ONLY)");
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}
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int main(int argc, char **argv)
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@ -1,19 +1,19 @@
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No TFI available.
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- Failed allocating TS=2, no USF available
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- Failed to allocate a TS, no USF available
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No TFI available.
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- Failed to allocate a TS, no USF available
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No TFI available.
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- Failed allocating TS=1, no USF available
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- Failed allocating TS=3, no USF available
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No suitable uplink slots available
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No suitable uplink slots available
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No suitable uplink slots available
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No suitable uplink slots available
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- Failed allocating TS=3, no USF available
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No TFI available.
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No suitable uplink slots available
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No TFI available.
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No TFI available.
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- Failed allocating TS=3, no USF available
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No TFI available.
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No suitable uplink slots available
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- Failed allocating TS=3, no USF available
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No TFI available.
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No suitable uplink slots available
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No TFI available.
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No TFI available.
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@ -8619,13 +8619,38 @@ Mass test: TS0(OOOOOOOO)TS7 MS_Class=28
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Mass test: TS0(OOOOOOOO)TS7 MS_Class=29
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Going to test assignment with many TBF, algorithm A (UL and DL)
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TBF[0] class 1 reserves ...C....
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TBF[1] class 1 reserves ...C....
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TBF[2] class 1 reserves ...C....
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TBF[3] class 1 reserves ...C....
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TBF[4] class 1 reserves ...C....
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TBF[1] class 1 reserves ....C...
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TBF[2] class 1 reserves .....C..
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TBF[3] class 1 reserves ......C.
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TBF[4] class 1 reserves .......C
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TBF[5] class 1 reserves ...C....
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TBF[6] class 1 reserves ...C....
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Successfully allocated 7 UL TBFs
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TBF[6] class 1 reserves ....C...
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TBF[7] class 1 reserves .....C..
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TBF[8] class 1 reserves ......C.
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TBF[9] class 1 reserves .......C
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TBF[10] class 1 reserves ...C....
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TBF[11] class 1 reserves ....C...
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TBF[12] class 1 reserves .....C..
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TBF[13] class 1 reserves ......C.
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TBF[14] class 1 reserves .......C
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TBF[15] class 1 reserves ...C....
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TBF[16] class 1 reserves ....C...
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TBF[17] class 1 reserves .....C..
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TBF[18] class 1 reserves ......C.
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TBF[19] class 1 reserves .......C
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TBF[20] class 1 reserves ...C....
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TBF[21] class 1 reserves ....C...
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TBF[22] class 1 reserves .....C..
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TBF[23] class 1 reserves ......C.
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TBF[24] class 1 reserves .......C
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TBF[25] class 1 reserves ...C....
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TBF[26] class 1 reserves ....C...
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TBF[27] class 1 reserves .....C..
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TBF[28] class 1 reserves ......C.
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TBF[29] class 1 reserves .......C
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TBF[30] class 1 reserves ...C....
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TBF[31] class 1 reserves ....C...
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Successfully allocated 32 UL TBFs
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Going to test assignment with many TBF, algorithm B class 10 (UL and DL)
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TBF[0] class 10 reserves ...DDCD.
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TBF[1] class 10 reserves ...DDCD.
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@ -8682,13 +8707,38 @@ Going to test assignment with many TBF, algorithm B class 1-29 (UL and DL)
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Successfully allocated 18 UL TBFs
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Going to test assignment with many TBF, algorithm A (DL and UL)
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TBF[0] class 1 reserves ...C....
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TBF[1] class 1 reserves ...C....
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TBF[2] class 1 reserves ...C....
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TBF[3] class 1 reserves ...C....
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TBF[4] class 1 reserves ...C....
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TBF[1] class 1 reserves ....C...
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TBF[2] class 1 reserves .....C..
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TBF[3] class 1 reserves ......C.
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TBF[4] class 1 reserves .......C
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TBF[5] class 1 reserves ...C....
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TBF[6] class 1 reserves ...C....
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Successfully allocated 7 UL TBFs
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TBF[6] class 1 reserves ....C...
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TBF[7] class 1 reserves .....C..
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TBF[8] class 1 reserves ......C.
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TBF[9] class 1 reserves .......C
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TBF[10] class 1 reserves ...C....
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TBF[11] class 1 reserves ....C...
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TBF[12] class 1 reserves .....C..
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TBF[13] class 1 reserves ......C.
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TBF[14] class 1 reserves .......C
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TBF[15] class 1 reserves ...C....
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TBF[16] class 1 reserves ....C...
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TBF[17] class 1 reserves .....C..
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TBF[18] class 1 reserves ......C.
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TBF[19] class 1 reserves .......C
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TBF[20] class 1 reserves ...C....
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TBF[21] class 1 reserves ....C...
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TBF[22] class 1 reserves .....C..
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TBF[23] class 1 reserves ......C.
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TBF[24] class 1 reserves .......C
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TBF[25] class 1 reserves ...C....
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TBF[26] class 1 reserves ....C...
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TBF[27] class 1 reserves .....C..
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TBF[28] class 1 reserves ......C.
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TBF[29] class 1 reserves .......C
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TBF[30] class 1 reserves ...C....
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TBF[31] class 1 reserves ....C...
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Successfully allocated 32 UL TBFs
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Going to test assignment with many TBF, algorithm B class 10 (DL and UL)
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TBF[0] class 10 reserves ...DDCD.
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TBF[1] class 10 reserves ...DDCD.
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@ -8700,37 +8750,37 @@ Going to test assignment with many TBF, algorithm B class 10 (DL and UL)
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Successfully allocated 7 UL TBFs
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Going to test assignment with many TBF, algorithm A (DL after UL)
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TBF[0] class 1 reserves ...C....
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TBF[1] class 1 reserves ...C....
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TBF[2] class 1 reserves ...C....
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TBF[3] class 1 reserves ...C....
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TBF[4] class 1 reserves ...C....
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TBF[1] class 1 reserves ....C...
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TBF[2] class 1 reserves .....C..
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TBF[3] class 1 reserves ......C.
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TBF[4] class 1 reserves .......C
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TBF[5] class 1 reserves ...C....
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TBF[6] class 1 reserves ...C....
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TBF[7] class 1 reserves ...C....
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TBF[8] class 1 reserves ...C....
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TBF[9] class 1 reserves ...C....
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TBF[6] class 1 reserves ....C...
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TBF[7] class 1 reserves .....C..
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TBF[8] class 1 reserves ......C.
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TBF[9] class 1 reserves .......C
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TBF[10] class 1 reserves ...C....
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TBF[11] class 1 reserves ...C....
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TBF[12] class 1 reserves ...C....
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TBF[13] class 1 reserves ...C....
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TBF[14] class 1 reserves ...C....
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TBF[11] class 1 reserves ....C...
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TBF[12] class 1 reserves .....C..
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TBF[13] class 1 reserves ......C.
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TBF[14] class 1 reserves .......C
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TBF[15] class 1 reserves ...C....
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TBF[16] class 1 reserves ...C....
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TBF[17] class 1 reserves ...C....
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TBF[18] class 1 reserves ...C....
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TBF[19] class 1 reserves ...C....
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TBF[16] class 1 reserves ....C...
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TBF[17] class 1 reserves .....C..
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TBF[18] class 1 reserves ......C.
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TBF[19] class 1 reserves .......C
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TBF[20] class 1 reserves ...C....
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TBF[21] class 1 reserves ...C....
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TBF[22] class 1 reserves ...C....
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TBF[23] class 1 reserves ...C....
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TBF[24] class 1 reserves ...C....
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TBF[21] class 1 reserves ....C...
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TBF[22] class 1 reserves .....C..
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TBF[23] class 1 reserves ......C.
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TBF[24] class 1 reserves .......C
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TBF[25] class 1 reserves ...C....
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TBF[26] class 1 reserves ...C....
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TBF[27] class 1 reserves ...C....
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TBF[28] class 1 reserves ...C....
|
||||
TBF[29] class 1 reserves ...C....
|
||||
TBF[26] class 1 reserves ....C...
|
||||
TBF[27] class 1 reserves .....C..
|
||||
TBF[28] class 1 reserves ......C.
|
||||
TBF[29] class 1 reserves .......C
|
||||
TBF[30] class 1 reserves ...C....
|
||||
TBF[31] class 1 reserves ...C....
|
||||
TBF[31] class 1 reserves ....C...
|
||||
Successfully allocated 32 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm B class 10 (DL after UL)
|
||||
TBF[0] class 10 reserves ...DDCD.
|
||||
|
|
@ -8768,13 +8818,38 @@ Going to test assignment with many TBF, algorithm B class 10 (DL after UL)
|
|||
Successfully allocated 32 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm A (UL after DL)
|
||||
TBF[0] class 1 reserves ...U....
|
||||
TBF[1] class 1 reserves ...U....
|
||||
TBF[2] class 1 reserves ...U....
|
||||
TBF[3] class 1 reserves ...U....
|
||||
TBF[4] class 1 reserves ...U....
|
||||
TBF[1] class 1 reserves ....U...
|
||||
TBF[2] class 1 reserves .....U..
|
||||
TBF[3] class 1 reserves ......U.
|
||||
TBF[4] class 1 reserves .......U
|
||||
TBF[5] class 1 reserves ...U....
|
||||
TBF[6] class 1 reserves ...U....
|
||||
Successfully allocated 7 UL TBFs
|
||||
TBF[6] class 1 reserves ....U...
|
||||
TBF[7] class 1 reserves .....U..
|
||||
TBF[8] class 1 reserves ......U.
|
||||
TBF[9] class 1 reserves .......U
|
||||
TBF[10] class 1 reserves ...U....
|
||||
TBF[11] class 1 reserves ....U...
|
||||
TBF[12] class 1 reserves .....U..
|
||||
TBF[13] class 1 reserves ......U.
|
||||
TBF[14] class 1 reserves .......U
|
||||
TBF[15] class 1 reserves ...U....
|
||||
TBF[16] class 1 reserves ....U...
|
||||
TBF[17] class 1 reserves .....U..
|
||||
TBF[18] class 1 reserves ......U.
|
||||
TBF[19] class 1 reserves .......U
|
||||
TBF[20] class 1 reserves ...U....
|
||||
TBF[21] class 1 reserves ....U...
|
||||
TBF[22] class 1 reserves .....U..
|
||||
TBF[23] class 1 reserves ......U.
|
||||
TBF[24] class 1 reserves .......U
|
||||
TBF[25] class 1 reserves ...U....
|
||||
TBF[26] class 1 reserves ....U...
|
||||
TBF[27] class 1 reserves .....U..
|
||||
TBF[28] class 1 reserves ......U.
|
||||
TBF[29] class 1 reserves .......U
|
||||
TBF[30] class 1 reserves ...U....
|
||||
TBF[31] class 1 reserves ....U...
|
||||
Successfully allocated 32 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm B class 10 (UL after DL)
|
||||
TBF[0] class 10 reserves .....U..
|
||||
TBF[1] class 10 reserves .....U..
|
||||
|
|
@ -8786,13 +8861,38 @@ Going to test assignment with many TBF, algorithm B class 10 (UL after DL)
|
|||
Successfully allocated 7 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm A (UL only)
|
||||
TBF[0] class 1 reserves ...U....
|
||||
TBF[1] class 1 reserves ...U....
|
||||
TBF[2] class 1 reserves ...U....
|
||||
TBF[3] class 1 reserves ...U....
|
||||
TBF[4] class 1 reserves ...U....
|
||||
TBF[1] class 1 reserves ....U...
|
||||
TBF[2] class 1 reserves .....U..
|
||||
TBF[3] class 1 reserves ......U.
|
||||
TBF[4] class 1 reserves .......U
|
||||
TBF[5] class 1 reserves ...U....
|
||||
TBF[6] class 1 reserves ...U....
|
||||
Successfully allocated 7 UL TBFs
|
||||
TBF[6] class 1 reserves ....U...
|
||||
TBF[7] class 1 reserves .....U..
|
||||
TBF[8] class 1 reserves ......U.
|
||||
TBF[9] class 1 reserves .......U
|
||||
TBF[10] class 1 reserves ...U....
|
||||
TBF[11] class 1 reserves ....U...
|
||||
TBF[12] class 1 reserves .....U..
|
||||
TBF[13] class 1 reserves ......U.
|
||||
TBF[14] class 1 reserves .......U
|
||||
TBF[15] class 1 reserves ...U....
|
||||
TBF[16] class 1 reserves ....U...
|
||||
TBF[17] class 1 reserves .....U..
|
||||
TBF[18] class 1 reserves ......U.
|
||||
TBF[19] class 1 reserves .......U
|
||||
TBF[20] class 1 reserves ...U....
|
||||
TBF[21] class 1 reserves ....U...
|
||||
TBF[22] class 1 reserves .....U..
|
||||
TBF[23] class 1 reserves ......U.
|
||||
TBF[24] class 1 reserves .......U
|
||||
TBF[25] class 1 reserves ...U....
|
||||
TBF[26] class 1 reserves ....U...
|
||||
TBF[27] class 1 reserves .....U..
|
||||
TBF[28] class 1 reserves ......U.
|
||||
TBF[29] class 1 reserves .......U
|
||||
TBF[30] class 1 reserves ...U....
|
||||
TBF[31] class 1 reserves ....U...
|
||||
Successfully allocated 32 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm B class 10 (UL only)
|
||||
TBF[0] class 10 reserves .....U..
|
||||
TBF[1] class 10 reserves .....U..
|
||||
|
|
@ -8804,37 +8904,37 @@ Going to test assignment with many TBF, algorithm B class 10 (UL only)
|
|||
Successfully allocated 7 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm A (DL ONLY)
|
||||
TBF[0] class 1 reserves ...C....
|
||||
TBF[1] class 1 reserves ...C....
|
||||
TBF[2] class 1 reserves ...C....
|
||||
TBF[3] class 1 reserves ...C....
|
||||
TBF[4] class 1 reserves ...C....
|
||||
TBF[1] class 1 reserves ....C...
|
||||
TBF[2] class 1 reserves .....C..
|
||||
TBF[3] class 1 reserves ......C.
|
||||
TBF[4] class 1 reserves .......C
|
||||
TBF[5] class 1 reserves ...C....
|
||||
TBF[6] class 1 reserves ...C....
|
||||
TBF[7] class 1 reserves ...C....
|
||||
TBF[8] class 1 reserves ...C....
|
||||
TBF[9] class 1 reserves ...C....
|
||||
TBF[6] class 1 reserves ....C...
|
||||
TBF[7] class 1 reserves .....C..
|
||||
TBF[8] class 1 reserves ......C.
|
||||
TBF[9] class 1 reserves .......C
|
||||
TBF[10] class 1 reserves ...C....
|
||||
TBF[11] class 1 reserves ...C....
|
||||
TBF[12] class 1 reserves ...C....
|
||||
TBF[13] class 1 reserves ...C....
|
||||
TBF[14] class 1 reserves ...C....
|
||||
TBF[11] class 1 reserves ....C...
|
||||
TBF[12] class 1 reserves .....C..
|
||||
TBF[13] class 1 reserves ......C.
|
||||
TBF[14] class 1 reserves .......C
|
||||
TBF[15] class 1 reserves ...C....
|
||||
TBF[16] class 1 reserves ...C....
|
||||
TBF[17] class 1 reserves ...C....
|
||||
TBF[18] class 1 reserves ...C....
|
||||
TBF[19] class 1 reserves ...C....
|
||||
TBF[16] class 1 reserves ....C...
|
||||
TBF[17] class 1 reserves .....C..
|
||||
TBF[18] class 1 reserves ......C.
|
||||
TBF[19] class 1 reserves .......C
|
||||
TBF[20] class 1 reserves ...C....
|
||||
TBF[21] class 1 reserves ...C....
|
||||
TBF[22] class 1 reserves ...C....
|
||||
TBF[23] class 1 reserves ...C....
|
||||
TBF[24] class 1 reserves ...C....
|
||||
TBF[21] class 1 reserves ....C...
|
||||
TBF[22] class 1 reserves .....C..
|
||||
TBF[23] class 1 reserves ......C.
|
||||
TBF[24] class 1 reserves .......C
|
||||
TBF[25] class 1 reserves ...C....
|
||||
TBF[26] class 1 reserves ...C....
|
||||
TBF[27] class 1 reserves ...C....
|
||||
TBF[28] class 1 reserves ...C....
|
||||
TBF[29] class 1 reserves ...C....
|
||||
TBF[26] class 1 reserves ....C...
|
||||
TBF[27] class 1 reserves .....C..
|
||||
TBF[28] class 1 reserves ......C.
|
||||
TBF[29] class 1 reserves .......C
|
||||
TBF[30] class 1 reserves ...C....
|
||||
TBF[31] class 1 reserves ...C....
|
||||
TBF[31] class 1 reserves ....C...
|
||||
Successfully allocated 32 UL TBFs
|
||||
Going to test assignment with many TBF, algorithm B class 10 (DL ONLY)
|
||||
TBF[0] class 10 reserves ...DDCD.
|
||||
|
|
|
|||
|
|
@ -4,6 +4,11 @@ Creating MS object, TLLI = 0x00000000
|
|||
Slot Allocation (Algorithm A) for class 0
|
||||
- Skipping TS 0, because not enabled
|
||||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 4, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Skipping TS 3, because num TBFs 0 >= 0
|
||||
- Assign downlink TS=2
|
||||
PDCH(TS 2, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 2
|
||||
|
|
@ -15,6 +20,11 @@ Allocating UL TBF: TFI=0 TRX=0 MS_CLASS=0
|
|||
Slot Allocation (Algorithm A) for class 0
|
||||
- Skipping TS 0, because not enabled
|
||||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 3, because not a downlink TBF
|
||||
- Skipping TS 4, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign uplink TS=2 USF=0
|
||||
PDCH(TS 2, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=UL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 2
|
||||
|
|
@ -34,6 +44,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -75,6 +88,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -90,6 +106,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE), 2 TBFs.
|
||||
TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE) Trigger dowlink assignment on PACCH, because another LLC PDU has arrived in between
|
||||
|
|
@ -117,6 +136,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -158,6 +180,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -173,6 +198,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE), 2 TBFs.
|
||||
TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE) Trigger dowlink assignment on PACCH, because another LLC PDU has arrived in between
|
||||
|
|
@ -200,6 +228,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -425,6 +456,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -441,6 +475,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -476,6 +513,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -499,6 +539,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -522,6 +565,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=2 TLLI=0x00000000 DIR=DL STATE=NULL), 3 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -545,6 +591,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=3 TLLI=0x00000000 DIR=DL STATE=NULL), 4 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -568,6 +617,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=4 TLLI=0x00000000 DIR=DL STATE=NULL), 5 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -591,6 +643,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=5 TLLI=0x00000000 DIR=DL STATE=NULL), 6 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -614,6 +669,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=6 TLLI=0x00000000 DIR=DL STATE=NULL), 7 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -637,6 +695,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=7 TLLI=0x00000000 DIR=DL STATE=NULL), 8 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -660,6 +721,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=8 TLLI=0x00000000 DIR=DL STATE=NULL), 9 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -683,6 +747,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=9 TLLI=0x00000000 DIR=DL STATE=NULL), 10 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -706,6 +773,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=10 TLLI=0x00000000 DIR=DL STATE=NULL), 11 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -729,6 +799,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=11 TLLI=0x00000000 DIR=DL STATE=NULL), 12 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -752,6 +825,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=12 TLLI=0x00000000 DIR=DL STATE=NULL), 13 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -775,6 +851,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=13 TLLI=0x00000000 DIR=DL STATE=NULL), 14 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -798,6 +877,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=14 TLLI=0x00000000 DIR=DL STATE=NULL), 15 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -821,6 +903,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=15 TLLI=0x00000000 DIR=DL STATE=NULL), 16 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -844,6 +929,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=16 TLLI=0x00000000 DIR=DL STATE=NULL), 17 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -867,6 +955,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=17 TLLI=0x00000000 DIR=DL STATE=NULL), 18 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -890,6 +981,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=18 TLLI=0x00000000 DIR=DL STATE=NULL), 19 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -913,6 +1007,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=19 TLLI=0x00000000 DIR=DL STATE=NULL), 20 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -936,6 +1033,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=20 TLLI=0x00000000 DIR=DL STATE=NULL), 21 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -959,6 +1059,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=21 TLLI=0x00000000 DIR=DL STATE=NULL), 22 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -982,6 +1085,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=22 TLLI=0x00000000 DIR=DL STATE=NULL), 23 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1005,6 +1111,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=23 TLLI=0x00000000 DIR=DL STATE=NULL), 24 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1028,6 +1137,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=24 TLLI=0x00000000 DIR=DL STATE=NULL), 25 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1051,6 +1163,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=25 TLLI=0x00000000 DIR=DL STATE=NULL), 26 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1074,6 +1189,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=26 TLLI=0x00000000 DIR=DL STATE=NULL), 27 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1097,6 +1215,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=27 TLLI=0x00000000 DIR=DL STATE=NULL), 28 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1120,6 +1241,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=28 TLLI=0x00000000 DIR=DL STATE=NULL), 29 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1143,6 +1267,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=29 TLLI=0x00000000 DIR=DL STATE=NULL), 30 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1166,6 +1293,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=30 TLLI=0x00000000 DIR=DL STATE=NULL), 31 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1189,6 +1319,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=31 TLLI=0x00000000 DIR=DL STATE=NULL), 32 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1215,6 +1348,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
@ -1241,6 +1377,9 @@ Slot Allocation (Algorithm A) for class 45
|
|||
- Skipping TS 1, because not enabled
|
||||
- Skipping TS 2, because not enabled
|
||||
- Skipping TS 3, because not enabled
|
||||
- Skipping TS 5, because not enabled
|
||||
- Skipping TS 6, because not enabled
|
||||
- Skipping TS 7, because not enabled
|
||||
- Assign downlink TS=4
|
||||
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
|
||||
- Setting Control TS 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue