109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __GDSYS_FPGA_H
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#define __GDSYS_FPGA_H
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enum {
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FPGA_STATE_DONE_FAILED = 1 << 0,
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FPGA_STATE_REFLECTION_FAILED = 1 << 1,
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};
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int get_fpga_state(unsigned dev);
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void print_fpga_state(unsigned dev);
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typedef struct ihs_gpio {
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u16 read;
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u16 clear;
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u16 set;
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} ihs_gpio_t;
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typedef struct ihs_i2c {
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u16 write_mailbox;
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u16 write_mailbox_ext;
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u16 read_mailbox;
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u16 read_mailbox_ext;
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} ihs_i2c_t;
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typedef struct ihs_osd {
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u16 version;
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u16 features;
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u16 control;
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u16 xy_size;
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} ihs_osd_t;
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#ifdef CONFIG_IO
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typedef struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[5]; /* 0x0008 */
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u16 quad_serdes_reset; /* 0x0012 */
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u16 reserved_1[8181]; /* 0x0014 */
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u16 reflection_high; /* 0x3ffe */
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} ihs_fpga_t;
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#endif
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#ifdef CONFIG_IOCON
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typedef struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[6]; /* 0x0008 */
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ihs_gpio_t gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_1[19]; /* 0x001c */
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u16 videocontrol; /* 0x0042 */
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u16 reserved_2[93]; /* 0x0044 */
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u16 reflection_high; /* 0x00fe */
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ihs_osd_t osd; /* 0x0100 */
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u16 reserved_3[892]; /* 0x0108 */
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u16 videomem; /* 0x0800 */
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} ihs_fpga_t;
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#endif
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#ifdef CONFIG_DLVISION_10G
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typedef struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[10]; /* 0x0008 */
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u16 extended_interrupt; /* 0x001c */
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u16 reserved_1[9]; /* 0x001e */
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ihs_i2c_t i2c; /* 0x0030 */
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u16 reserved_2[35]; /* 0x0038 */
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u16 reflection_high; /* 0x007e */
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u16 reserved_3[15]; /* 0x0080 */
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u16 videocontrol; /* 0x009e */
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u16 reserved_4[176]; /* 0x00a0 */
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ihs_osd_t osd; /* 0x0200 */
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u16 reserved_5[764]; /* 0x0208 */
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u16 videomem; /* 0x0800 */
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} ihs_fpga_t;
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#endif
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#endif
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