565 lines
12 KiB
C
565 lines
12 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#define CRAM_BANK0_BASE 0x0
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#define CRAM_DIDR 0x00100000
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#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
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#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
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#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
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#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
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#define CRAM_DEVID_NOT_SUPPORTED 0x00000000
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#define PSRAM_PASS 0x50415353 /* "PASS" */
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#define PSRAM_FAIL 0x4641494C /* "FAIL" */
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static u32 is_cram_inited(void);
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static u32 is_cram(void);
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static long int cram_init(u32);
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static void cram_bcr_write(u32);
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void udelay (unsigned long);
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void sdram_init(void)
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{
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volatile unsigned long spr_reg;
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/*
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* If CRAM not initialized or CRAM looks initialized because this
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* is after a warm reboot then set SPRG7 to indicate CRAM needs
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* initialization. Note that CRAM is initialized by the SPI and
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* NAND preloader.
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*/
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spr_reg = (volatile unsigned long) mfspr(SPRG6);
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if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
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mtspr(SPRG7, LOAK_NONE); /* "NONE" */
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}
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#if 1
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/*
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* When running the NAND SPL, the normal EBC configuration is not
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* done, so We need to enable EPLD access on EBC_CS_2 and the memory
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* on EBC_CS_3
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*/
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/* Enable CPLD - Needed for PSRAM Access */
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/* Init SDRAM by setting EBC Bank 3 for PSRAM */
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mtebc(pb1ap, CFG_EBC_PB1AP);
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mtebc(pb1cr, CFG_EBC_PB1CR);
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mtebc(pb2ap, CFG_EBC_PB2AP);
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mtebc(pb2cr, CFG_EBC_PB2CR);
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/* pre-boot loader code: we are in OCM */
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mtspr(SPRG6, LOAK_SPL); /* "SPL " */
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mtspr(SPRG7, LOAK_OCM); /* "OCM " */
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#endif
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return;
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}
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static void cram_bcr_write(u32 wr_val)
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{
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u32 tmp_reg;
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u32 val;
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volatile u32 gpio_reg;
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/* # Program CRAM write */
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/*
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* set CRAM_CRE = 0x1
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* set wr_val = wr_val << 2
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*/
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gpio_reg = in32(GPIO1_OR);
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out32(GPIO1_OR, gpio_reg | 0x00000400);
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wr_val = wr_val << 2;
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/* wr_val = 0x1c048; */
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/*
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* # stop PLL clock before programming CRAM
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* set EPLD0_MUX_CTL.OESPR3 = 1
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* delay 2
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*/
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/*
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* # CS1
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* read 0x00200000
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* #shift 2 bit left before write
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* set val = wr_val + 0x00200000
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* write dmem val 0
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* read 0x00200000 val
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* print val/8x
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*/
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tmp_reg = in32(0x00200000);
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val = wr_val + 0x00200000;
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/* val = 0x0021c048; */
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out32(val, 0x0000);
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udelay(100000);
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val = in32(0x00200000);
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debug("CRAM VAL: %x for CS1 ", val);
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/*
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* # CS2
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* read 0x02200000
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* #shift 2 bit left before write
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* set val = wr_val + 0x02200000
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* write dmem val 0
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* read 0x02200000 val
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* print val/8x
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*/
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tmp_reg = in32(0x02200000);
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val = wr_val + 0x02200000;
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/* val = 0x0221c048; */
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out32(val, 0x0000);
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udelay(100000);
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val = in32(0x02200000);
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debug("CRAM VAL: %x for CS2 ", val);
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/*
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* # Start PLL clock before programming CRAM
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* set EPLD0_MUX_CTL.OESPR3 = 0
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*/
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/*
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* set CRAMCR = 0x1
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*/
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gpio_reg = in32(GPIO1_OR);
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out32(GPIO1_OR, gpio_reg | 0x00000400);
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/*
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* # read CRAM config BCR ( bit19:18 = 10b )
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* #read 0x00200000
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* # 1001_1001_0001_1111 ( 991f ) =>
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* #10_0110_0100_0111_1100 => 2647c => 0022647c
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* #0011_0010_0011_1110 (323e)
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* #
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*/
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/*
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* set EPLD0_MUX_CTL.CRAMCR = 0x0
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*/
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gpio_reg = in32(GPIO1_OR);
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out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
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return;
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}
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static u32 is_cram_inited()
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{
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volatile unsigned long spr_reg;
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/*
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* If CRAM is initialized already, then don't reinitialize it again.
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* In the case of NAND boot and SPI boot, CRAM will already be
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* initialized by the pre-loader
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*/
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spr_reg = (volatile unsigned long) mfspr(SPRG7);
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if (spr_reg == LOAK_CRAM) {
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return 1;
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} else {
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return 0;
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}
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}
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/******
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* return 0 if not CRAM
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* return 1 if CRAM and it's already inited by preloader
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* else return cram_id (CRAM Device Identification Register)
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******/
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static u32 is_cram(void)
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{
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u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
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volatile u32 gpio_reg;
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volatile u32 cram_id = 0;
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if (is_cram_inited() == 1) {
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/* this is CRAM and it is already inited (by preloader) */
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cram_id = 1;
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} else {
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/*
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* # CRAM CLOCK
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* set GPIO0_TCR.G8 = 1
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* set GPIO0_OSRL.G8 = 0
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* set GPIO0_OR.G8 = 0
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*/
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gpio_reg = in32(GPIO0_TCR);
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gpio_TCR = gpio_reg;
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out32(GPIO0_TCR, gpio_reg | 0x00800000);
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gpio_reg = in32(GPIO0_OSRL);
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gpio_OSRL = gpio_reg;
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out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
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gpio_reg = in32(GPIO0_OR);
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gpio_OR = gpio_reg;
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out32(GPIO0_OR, gpio_reg & 0xff7fffff);
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/*
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* # CRAM Addreaa Valid
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* set GPIO0_TCR.G10 = 1
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* set GPIO0_OSRL.G10 = 0
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* set GPIO0_OR.G10 = 0
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*/
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gpio_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, gpio_reg | 0x00200000);
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gpio_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
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gpio_reg = in32(GPIO0_OR);
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out32(GPIO0_OR, gpio_reg & 0xffdfffff);
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/*
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* # config input (EBC_WAIT)
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* set GPIO0_ISR1L.G9 = 1
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* set GPIO0_TCR.G9 = 0
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*/
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gpio_reg = in32(GPIO0_ISR1L);
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gpio_ISR1L = gpio_reg;
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out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
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gpio_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
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/*
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* Enable CRE to read Registers
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* set GPIO0_TCR.21 = 1
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* set GPIO1_OR.21 = 1
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*/
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gpio_reg = in32(GPIO1_TCR);
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out32(GPIO1_TCR, gpio_reg | 0x00000400);
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gpio_reg = in32(GPIO1_OR);
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out32(GPIO1_OR, gpio_reg | 0x00000400);
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/* Read Version ID */
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cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
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udelay(100000);
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asm volatile(" sync");
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asm volatile(" eieio");
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debug("Cram ID: %X ", cram_id);
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switch (cram_id) {
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case MICRON_MT45W8MW16BGX_CRAM_ID:
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case MICRON_MT45W8MW16BGX_CRAM_ID2:
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/* supported CRAM vendor/part */
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break;
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case CRAM_DEVID_NOT_SUPPORTED:
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default:
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/* check for DIDR Vendor ID of Micron */
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if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
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MICRON_DIDR_VENDOR_ID)
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{
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/* supported CRAM vendor */
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break;
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}
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/* this is not CRAM or not supported CRAM vendor/part */
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cram_id = 0;
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/*
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* reset the GPIO registers to the values that were
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* there before this routine
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*/
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out32(GPIO0_TCR, gpio_TCR);
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out32(GPIO0_OSRL, gpio_OSRL);
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out32(GPIO0_OR, gpio_OR);
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out32(GPIO0_ISR1L, gpio_ISR1L);
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break;
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}
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}
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return cram_id;
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}
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static long int cram_init(u32 already_inited)
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{
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volatile u32 tmp_reg;
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u32 cram_wr_val;
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if (already_inited == 0) return 0;
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/*
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* If CRAM is initialized already, then don't reinitialize it again.
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* In the case of NAND boot and SPI boot, CRAM will already be
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* initialized by the pre-loader
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*/
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if (already_inited != 1)
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{
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/*
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* #o CRAM Card
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* # - CRAMCRE @reg16 = 1; for CRAM to use
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* # - CRAMCRE @reg16 = 0; for CRAM to program
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*
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* # enable CRAM SEL, move from setEPLD.cmd
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* set EPLD0_MUX_CTL.OECRAM = 0
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* set EPLD0_MUX_CTL.CRAMCR = 1
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* set EPLD0_ETHRSTBOOT.SLCRAM = 0
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* #end
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*/
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/*
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* #1. EBC need to program READY, CLK, ADV for ASync mode
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* # config output
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*/
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/*
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* # CRAM CLOCK
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* set GPIO0_TCR.G8 = 1
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* set GPIO0_OSRL.G8 = 0
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* set GPIO0_OR.G8 = 0
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*/
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg | 0x00800000);
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tmp_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
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tmp_reg = in32(GPIO0_OR);
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out32(GPIO0_OR, tmp_reg & 0xff7fffff);
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/*
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* # CRAM Addreaa Valid
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* set GPIO0_TCR.G10 = 1
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* set GPIO0_OSRL.G10 = 0
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* set GPIO0_OR.G10 = 0
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*/
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg | 0x00200000);
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tmp_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
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tmp_reg = in32(GPIO0_OR);
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out32(GPIO0_OR, tmp_reg & 0xffdfffff);
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/*
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* # config input (EBC_WAIT)
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* set GPIO0_ISR1L.G9 = 1
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* set GPIO0_TCR.G9 = 0
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*/
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tmp_reg = in32(GPIO0_ISR1L);
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out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
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/*
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* # config CS4 from GPIO
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* set GPIO0_TCR.G0 = 1
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* set GPIO0_OSRL.G0 = 1
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*/
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg | 0x80000000);
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tmp_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, tmp_reg | 0x40000000);
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/*
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* #2. EBC in Async mode
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* # set EBC0_PB1AP = 0x078f0ec0
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* set EBC0_PB1AP = 0x078f1ec0
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* set EBC0_PB2AP = 0x078f1ec0
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*/
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mtebc(pb1ap, 0x078F1EC0);
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mtebc(pb2ap, 0x078F1EC0);
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/*
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* #set EBC0_PB1CR = 0x000bc000
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* #enable CS2 for CRAM
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* set EBC0_PB2CR = 0x020bc000
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*/
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mtebc(pb1cr, 0x000BC000);
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mtebc(pb2cr, 0x020BC000);
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/*
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* #3. set CRAM in Sync mode
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* #exec cm_bcr_write.cmd { 0x701f }
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* #3. set CRAM in Sync mode (full drv strength)
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* exec cm_bcr_write.cmd { 0x701F }
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*/
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cram_wr_val = 0x7012; /* CRAM burst setting */
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cram_bcr_write(cram_wr_val);
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/*
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* #4. EBC in Sync mode
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* #set EBC0_PB1AP = 0x9f800fc0
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* #set EBC0_PB1AP = 0x900001c0
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* set EBC0_PB2AP = 0x9C0201c0
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* set EBC0_PB2AP = 0x9C0201c0
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*/
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mtebc(pb1ap, 0x9C0201C0);
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mtebc(pb2ap, 0x9C0201C0);
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/*
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* #5. EBC need to program READY, CLK, ADV for Sync mode
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* # config output
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* set GPIO0_TCR.G8 = 1
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* set GPIO0_OSRL.G8 = 1
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* set GPIO0_TCR.G10 = 1
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* set GPIO0_OSRL.G10 = 1
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*/
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg | 0x00800000);
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tmp_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, tmp_reg | 0x00004000);
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg | 0x00200000);
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tmp_reg = in32(GPIO0_OSRL);
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out32(GPIO0_OSRL, tmp_reg | 0x00000400);
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/*
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* # config input
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* set GPIO0_ISR1L.G9 = 1
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* set GPIO0_TCR.G9 = 0
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*/
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tmp_reg = in32(GPIO0_ISR1L);
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out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
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tmp_reg = in32(GPIO0_TCR);
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out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
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/*
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* # config EBC to use RDY
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* set SDR0_ULTRA0.EBCREN = 1
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*/
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mfsdr(sdrultra0, tmp_reg);
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mtsdr(sdrultra0, tmp_reg | 0x04000000);
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/*
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* set EPLD0_MUX_CTL.OESPR3 = 0
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*/
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mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
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} /* if (already_inited != 1) */
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return (64 * 1024 * 1024);
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}
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/******
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* return 0 if not PSRAM
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* return 1 if is PSRAM
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******/
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static int is_psram(u32 addr)
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{
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u32 test_pattern = 0xdeadbeef;
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volatile u32 readback;
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if (addr == CFG_SDRAM_BASE) {
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/* This is to temp enable OE for PSRAM */
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out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
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udelay(10000);
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}
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out32(addr, test_pattern);
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asm volatile(" sync");
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asm volatile(" eieio");
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readback = (volatile u32) in32(addr);
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asm volatile(" sync");
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asm volatile(" eieio");
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if (readback == test_pattern) {
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return 1;
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} else {
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return 0;
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}
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}
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static long int psram_init(void)
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{
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u32 readback;
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long psramsize = 0;
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int i;
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/* This is to temp enable OE for PSRAM */
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out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
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udelay(10000);
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/*
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* PSRAM bank 1: read then write to address 0x00000000
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*/
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for (i = 0; i < 100; i++) {
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if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
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readback = PSRAM_PASS;
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} else {
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|
readback = PSRAM_FAIL;
|
|
break;
|
|
}
|
|
}
|
|
if (readback == PSRAM_PASS) {
|
|
debug("psram_init(bank0): pass\n");
|
|
psramsize = (16 * 1024 * 1024);
|
|
} else {
|
|
debug("psram_init(bank0): fail\n");
|
|
return 0;
|
|
}
|
|
|
|
#if 0
|
|
/*
|
|
* PSRAM bank 1: read then write to address 0x01000000
|
|
*/
|
|
for (i = 0; i < 100; i++) {
|
|
if (is_psram((1 << 24) + (i*256)) == 1) {
|
|
readback = PSRAM_PASS;
|
|
} else {
|
|
readback = PSRAM_FAIL;
|
|
break;
|
|
}
|
|
}
|
|
if (readback == PSRAM_PASS) {
|
|
debug("psram_init(bank1): pass\n");
|
|
psramsize = psramsize + (16 * 1024 * 1024);
|
|
}
|
|
#endif
|
|
|
|
mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
|
|
|
|
return psramsize;
|
|
}
|
|
|
|
long int initdram(int board_type)
|
|
{
|
|
long int sram_size;
|
|
u32 cram_inited;
|
|
|
|
/* Determine Attached Memory Expansion Card*/
|
|
cram_inited = is_cram();
|
|
if (cram_inited != 0) { /* CRAM */
|
|
debug("CRAM Expansion Card attached\n");
|
|
sram_size = cram_init(cram_inited);
|
|
} else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
|
|
debug("PSRAM Expansion Card attached\n");
|
|
sram_size = psram_init();
|
|
} else { /* no SRAM */
|
|
debug("No Memory Card Attached!!\n");
|
|
sram_size = 0;
|
|
}
|
|
|
|
return sram_size;
|
|
}
|
|
|
|
int testdram(void)
|
|
{
|
|
return (0);
|
|
}
|