222 lines
4.8 KiB
ArmAsm
222 lines
4.8 KiB
ArmAsm
/*
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* (C) 2010 by Tieto <www.tieto.com>
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* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <config.h>
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#include <asm/arch-mtk/mt6235.h>
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#include <asm/arch-mtk/emi.h>
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#include <asm/arch-mtk/system.h>
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.globl lowlevel_init
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.type lowlevel_init,function
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lowlevel_init:
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/* -----------------------------
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* Initialize PLL
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* -----------------------------
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*/
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/* Power on PLL */
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ldr r0, =MTK_PLL_PDN_CON
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mov r1, #0
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str r1, [r0]
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/* Turn on MCU and DSP dividers, mark that SYSCLK is 26MHz */
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ldr r0, =MTK_PLL_CLK_CON
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mov r1, #0x83
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str r1, [r0]
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/* Reset PLL */
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ldr r0, =MTK_PLL_PLL
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mov r1, #0x80
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str r1, [r0]
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mov r1, #0
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str r1, [r0]
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mov r1, #0xFF
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PLL_DELAY_loop:
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subs r1, r1, #1
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bgt PLL_DELAY_loop
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/* Turn on PLL for MCU, DSP and USB */
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mov r1, #0x70
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str r1, [r0]
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/*
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* Setup MCU clock register:
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* ARMCLK = 208MHz, AHBx4CLK = 52MHz, AHBx8CLK = 104MHz
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* we have to write to the read-only part (EMICLK) as well, otherwise
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* the EMI won't work! (datasheet lies)
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*/
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ldr r0, =MTK_CONFG_MCUCLK_CON
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ldr r1, =0x7F37
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str r1, [r0]
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/* -----------------------------
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* Initialize SDRAM controller
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* -----------------------------
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*/
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/* Reset index of SDRAM config table */
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mov r7, #0
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SDRAM_TRY_CONFIG:
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adr r1, SDRAM_CONFIG_TABLE
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/* Calculate config table offset (index * element_size) */
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lsl r2, r7, #3
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/* Calculate address of element in config table */
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add r1, r1, r2
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/* Load start address of SDRAM configuration */
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ldr r0, [r1]
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/* Check if end of SDRAM config table is reached */
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cmp r0, #0
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beq SDRAM_PASSED
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/* Load end address of SDRAM configuration */
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ldr r6, [r1, #4]
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/* Configure SDRAM controller */
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SDRAM_REGSET_LOOP:
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ldr r1, [r0]
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ldr r2, [r0, #4]
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str r1, [r2]
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add r0, r0, #8
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mov r1, #0xFF
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SDRAM_DELAY_LOOP:
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subs r1, r1, #1
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bgt SDRAM_DELAY_LOOP
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cmp r0, r6
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blt SDRAM_REGSET_LOOP
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/* Perform test to check if SDRAM is properly configured */
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mov r0, #0x1000
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mov r1, #0x0
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mov r2, #16384
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SDRAM_WRITE_LOOP:
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str r1, [r0]
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add r0, r0, #4
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add r1, r1, #1
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cmp r1, r2
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blt SDRAM_WRITE_LOOP
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mov r0, #0x1000
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mov r3, #0x0
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SDRAM_VERIFY_LOOP:
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ldr r1, [r0]
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add r0, r0, #4
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cmp r1, r3
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bne SDRAM_FAILED
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add r3, r3, #1
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cmp r3, r2
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blt SDRAM_VERIFY_LOOP
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SDRAM_PASSED:
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/* return from function */
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mov pc, lr
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/* SDRAM configuration failed, try another one */
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SDRAM_FAILED:
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/* Increment SDRAM config table index */
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add r7, r7, #1
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b SDRAM_TRY_CONFIG
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SDRAM_CONFIG_TABLE:
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.word SDRAM_64MB_CONFIG
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.word SDRAM_64MB_CONFIG_END
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.word SDRAM_32MB_CONFIG
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.word SDRAM_32MB_CONFIG_END
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.word 0
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/* This configuration is for 64MB SDRAM memory */
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SDRAM_64MB_CONFIG:
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.word 0x00088E3A
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.word MTK_EMI_GENA
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.word 0x000000C0
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.word MTK_EMI_GENB
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.word 0x18C618C6
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.word MTK_EMI_GENC
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.word 0x0001000E
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.word MTK_EMI_GEND
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.word 0x00332000
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.word MTK_EMI_CONI
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.word 0x3CD24431
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.word MTK_EMI_CONJ
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.word 0x02000000
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.word MTK_EMI_CONK
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.word 0x18007505
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.word MTK_EMI_CONL
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.word 0x00002828
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.word MTK_EMI_CONM
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.word 0x1500013
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.word MTK_EMI_CONN
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.word 0x500013
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.word MTK_EMI_CONN
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.word 0x2500013
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.word MTK_EMI_CONN
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.word 0x500013
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.word MTK_EMI_CONN
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.word 0x4500013
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.word MTK_EMI_CONN
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.word 0x500013
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.word MTK_EMI_CONN
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.word 0x8500013
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.word MTK_EMI_CONN
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.word 0x500013
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.word MTK_EMI_CONN
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.word 0x80500013
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.word MTK_EMI_CONN
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.word 0x500013
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.word MTK_EMI_CONN
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SDRAM_64MB_CONFIG_END:
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/* This configuration is for 32MB SDRAM memory */
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SDRAM_32MB_CONFIG:
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.word 0x00088a0a
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.word MTK_EMI_GENA
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.word 0x00000280
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.word MTK_EMI_GENB
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.word 0x52945294
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.word MTK_EMI_GENC
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.word 0x0001000E
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.word MTK_EMI_GEND
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.word 0x02334000
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.word MTK_EMI_CONI
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.word 0x16c12212
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.word MTK_EMI_CONJ
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.word 0x032d0000
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.word MTK_EMI_CONK
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.word 0x1c016605
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.word MTK_EMI_CONL
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.word 0x00002828
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.word MTK_EMI_CONM
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.word 0x1400013
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.word MTK_EMI_CONN
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.word 0x400013
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.word MTK_EMI_CONN
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.word 0x2400013
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.word MTK_EMI_CONN
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.word 0x400013
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.word MTK_EMI_CONN
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.word 0x4400013
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.word MTK_EMI_CONN
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.word 0x400013
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.word MTK_EMI_CONN
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.word 0x8400013
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.word MTK_EMI_CONN
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.word 0x400013
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.word MTK_EMI_CONN
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.word 0x80400013
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.word MTK_EMI_CONN
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.word 0x400013
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.word MTK_EMI_CONN
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SDRAM_32MB_CONFIG_END:
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