192 lines
5.2 KiB
ArmAsm
192 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2009 Wind River Systems, Inc.
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* Tom Rix <Tom.Rix@windriver.com>
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*
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* This file is based on and replaces the existing cache.c file
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* The copyrights for the cache.c file are:
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*
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* (C) Copyright 2008 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/omap3.h>
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/*
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* omap3 cache code
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*/
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.align 5
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.global invalidate_dcache
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.global l2_cache_enable
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.global l2_cache_disable
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/*
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* invalidate_dcache()
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*
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* Invalidate the whole D-cache.
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*
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* Corrupted registers: r0-r5, r7, r9-r11
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*
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* - mm - mm_struct describing address space
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*/
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invalidate_dcache:
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stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
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mov r7, r0 @ take a backup of device type
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cmp r0, #0x3 @ check if the device type is
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@ GP
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moveq r12, #0x1 @ set up to invalide L2
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smi: .word 0x01600070 @ Call SMI monitor (smieq)
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cmp r7, #0x3 @ compare again in case its
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@ lost
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beq finished_inval @ if GP device, inval done
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@ above
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished_inval @ if loc is 0, then no need to
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@ clean
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mov r10, #0 @ start clean at cache level 0
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inval_loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache
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@ level
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mov r1, r0, lsr r2 @ extract cache type bits from
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@ clidr
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and r1, r1, #7 @ mask of the bits for current
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@ cache only
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cmp r1, #2 @ see what cache we have at
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@ this level
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blt skip_inval @ skip if no cache, or just
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@ i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mov r2, #0 @ operand for mcr SBZ
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mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
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@ sych the new cssr&csidr,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the
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@ cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the
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@ way size
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clz r5, r4 @ find bit position of way
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@ size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the
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@ index size
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inval_loop2:
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mov r9, r4 @ create working copy of max
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@ way size
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inval_loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number
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@ into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge inval_loop3
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subs r7, r7, #1 @ decrement the index
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bge inval_loop2
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skip_inval:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt inval_loop1
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finished_inval:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
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l2_cache_enable:
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stmfd r13!, {r0, r1, r2, lr}
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@ ES2 onwards we can disable/enable L2 ourselves
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bl get_cpu_rev
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cmp r0, #CPU_3XX_ES20
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blt l2_cache_disable_EARLIER_THAN_ES2
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mrc 15, 0, r3, cr1, cr0, 1
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orr r3, r3, #2
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mcr 15, 0, r3, cr1, cr0, 1
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b l2_cache_enable_END
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l2_cache_enable_EARLIER_THAN_ES2:
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@ Save r0, r12 and restore them after usage
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mov r3, ip
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str r3, [sp, #4]
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mov r3, r0
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@
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@ GP Device ROM code API usage here
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@ r12 = AUXCR Write function and r0 value
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@
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mov ip, #3
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mrc 15, 0, r0, cr1, cr0, 1
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orr r0, r0, #2
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@ SMI instruction to call ROM Code API
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.word 0xe1600070
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mov r0, r3
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mov ip, r3
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str r3, [sp, #4]
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l2_cache_enable_END:
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ldmfd r13!, {r1, r2, r3, pc}
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l2_cache_disable:
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stmfd r13!, {r0, r1, r2, lr}
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@ ES2 onwards we can disable/enable L2 ourselves
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bl get_cpu_rev
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cmp r0, #CPU_3XX_ES20
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blt l2_cache_disable_EARLIER_THAN_ES2
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mrc 15, 0, r3, cr1, cr0, 1
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bic r3, r3, #2
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mcr 15, 0, r3, cr1, cr0, 1
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b l2_cache_disable_END
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l2_cache_disable_EARLIER_THAN_ES2:
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@ Save r0, r12 and restore them after usage
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mov r3, ip
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str r3, [sp, #4]
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mov r3, r0
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@
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@ GP Device ROM code API usage here
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@ r12 = AUXCR Write function and r0 value
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@
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mov ip, #3
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mrc 15, 0, r0, cr1, cr0, 1
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bic r0, r0, #2
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@ SMI instruction to call ROM Code API
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.word 0xe1600070
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mov r0, r3
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mov ip, r3
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str r3, [sp, #4]
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l2_cache_disable_END:
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ldmfd r13!, {r1, r2, r3, pc}
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