473 lines
17 KiB
C
473 lines
17 KiB
C
/*
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* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
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*
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* (C) Copyright 2006
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* Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/fsl_upm.h>
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#include <ioports.h>
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#include <nand.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern uint get_lbc_clock (void);
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/* index of UPM RAM array run pattern for NAND command cycle */
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#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08
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/* index of UPM RAM array run pattern for NAND address cycle */
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#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10
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/* Structure for table with supported UPM timings */
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struct upm_freq {
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ulong freq;
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const u32 *upm_patt;
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uchar gpl4_disable;
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uchar ehtr;
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uchar ead;
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};
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/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
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/* UPM pattern for bus clock = 25 MHz */
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static const u32 upm_patt_25[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 33.3 MHz */
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static const u32 upm_patt_33[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 41.7 MHz */
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static const u32 upm_patt_42[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 50 MHz */
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static const u32 upm_patt_50[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 66.7 MHz */
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static const u32 upm_patt_67[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 83.3 MHz */
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static const u32 upm_patt_83[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 100 MHz */
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static const u32 upm_patt_100[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 133.3 MHz */
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static const u32 upm_patt_133[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
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/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Exception RAM array entry -> unsused */
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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/* UPM pattern for bus clock = 166.7 MHz */
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static const u32 upm_patt_167[] = {
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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/* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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/* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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/* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* UPM Write Burst RAM array entry -> unused */
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* UPM Refresh Timer RAM array entry -> unused */
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
|
|
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
|
|
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
|
|
|
/* UPM Exception RAM array entry -> unsused */
|
|
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
|
|
};
|
|
|
|
/* Supported UPM timings */
|
|
struct upm_freq upm_freq_table[] = {
|
|
/* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */
|
|
{25000000, upm_patt_25, 1, 0, 0},
|
|
{33333333, upm_patt_33, 1, 0, 0},
|
|
{41666666, upm_patt_42, 1, 0, 0},
|
|
{50000000, upm_patt_50, 0, 0, 0},
|
|
{66666666, upm_patt_67, 0, 0, 0},
|
|
{83333333, upm_patt_83, 0, 0, 0},
|
|
{100000000, upm_patt_100, 0, 1, 1},
|
|
{133333333, upm_patt_133, 0, 1, 1},
|
|
{166666666, upm_patt_167, 0, 1, 1},
|
|
};
|
|
|
|
#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
|
|
|
|
volatile const u32 *nand_upm_patt;
|
|
|
|
/*
|
|
* write into UPMB ram
|
|
*/
|
|
static void upmb_write (u_char addr, ulong val)
|
|
{
|
|
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
|
|
|
out_be32 (&lbc->mdr, val);
|
|
|
|
clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
|
|
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
|
|
|
|
/* dummy access to perform write */
|
|
out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
|
|
|
|
clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
|
|
}
|
|
|
|
/*
|
|
* Initialize UPM for NAND flash access.
|
|
*/
|
|
static void nand_upm_setup (volatile fsl_lbc_t *lbc)
|
|
{
|
|
uint i, j;
|
|
uint or3 = CONFIG_SYS_OR3_PRELIM;
|
|
uint clock = get_lbc_clock ();
|
|
|
|
set_lbc_br(3, 0); /* disable bank and reset all bits */
|
|
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
|
|
|
|
/*
|
|
* Search appropriate UPM table for bus clock.
|
|
* If the bus clock exceeds a tolerated value, take the UPM timing for
|
|
* the next higher supported frequency to ensure that access works
|
|
* (even the access may be slower then).
|
|
*/
|
|
for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
|
|
;
|
|
|
|
if (i >= UPM_FREQS)
|
|
/* no valid entry found */
|
|
/* take last entry with configuration for max. bus clock */
|
|
i--;
|
|
|
|
if (upm_freq_table[i].ehtr) {
|
|
/* EHTR must be set due to TQM8548 timing specification */
|
|
or3 |= OR_UPM_EHTR;
|
|
}
|
|
if (upm_freq_table[i].ead)
|
|
/* EAD must be set due to TQM8548 timing specification */
|
|
or3 |= OR_UPM_EAD;
|
|
|
|
set_lbc_or(3, or3);
|
|
|
|
/* Assign address of table */
|
|
nand_upm_patt = upm_freq_table[i].upm_patt;
|
|
|
|
for (j = 0; j < 64; j++) {
|
|
upmb_write (j, *nand_upm_patt);
|
|
nand_upm_patt++;
|
|
}
|
|
|
|
/* Put UPM back to normal operation mode */
|
|
if (upm_freq_table[i].gpl4_disable)
|
|
/* GPL4 must be disabled according to timing specification */
|
|
out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
|
|
|
|
return;
|
|
}
|
|
|
|
static struct fsl_upm_nand fun = {
|
|
.width = 8,
|
|
.upm_cmd_offset = 0x08,
|
|
.upm_addr_offset = 0x10,
|
|
.upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
|
|
.chip_offset = CONFIG_SYS_NAND_CS_DIST,
|
|
.chip_delay = NAND_BIG_DELAY_US,
|
|
.wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
|
|
};
|
|
|
|
void board_nand_select_device (struct nand_chip *nand, int chip)
|
|
{
|
|
}
|
|
|
|
int board_nand_init (struct nand_chip *nand)
|
|
{
|
|
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
|
|
|
if (!nand_upm_patt)
|
|
nand_upm_setup (lbc);
|
|
|
|
fun.upm.io_addr = nand->IO_ADDR_R;
|
|
fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
|
|
fun.upm.mdr = (void __iomem *)&lbc->mdr;
|
|
fun.upm.mar = (void __iomem *)&lbc->mar;
|
|
|
|
return fsl_upm_nand_init (nand, &fun);
|
|
}
|