152 lines
3.2 KiB
C
152 lines
3.2 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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/*
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* CPU specific code for the MPC83xx family.
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*
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* Derived from the MPC8260 and MPC85xx.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc83xx.h>
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#include <asm/processor.h>
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int checkcpu(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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ulong clock = gd->cpu_clk;
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u32 pvr = get_pvr();
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char buf[32];
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if ((pvr & 0xFFFF0000) != PVR_83xx) {
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puts("Not MPC83xx Family!!!\n");
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return -1;
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}
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puts("CPU: MPC83xx, ");
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switch(pvr) {
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case PVR_8349_REV10:
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break;
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case PVR_8349_REV11:
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break;
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default:
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puts("Rev: Unknown\n");
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return -1; /* Not sure what this is */
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}
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printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
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return 0;
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}
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void upmconfig (uint upm, uint *table, uint size)
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{
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hang(); /* FIXME: upconfig() needed? */
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}
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong msr;
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#ifndef MPC83xx_RESET
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ulong addr;
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#endif
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
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#ifdef MPC83xx_RESET
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~( MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* enable Reset Control Reg */
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immap->reset.rpr = 0x52535445;
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/* confirm Reset Control Reg is enabled */
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while(!((immap->reset.rcer) & RCER_CRE));
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printf("Resetting the board.");
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printf("\n");
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udelay(200);
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/* perform reset, only one bit */
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immap->reset.rcr = RCR_SWHR;
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#else /* ! MPC83xx_RESET */
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immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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addr = CFG_RESET_ADDRESS;
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printf("resetting the board.");
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printf("\n");
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((void (*)(void)) addr) ();
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#endif /* MPC83xx_RESET */
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return 1;
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}
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*/
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unsigned long get_tbclk(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return tbclk;
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}
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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hang(); /* FIXME: implement watchdog_reset()? */
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}
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#endif /* CONFIG_WATCHDOG */
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