452 lines
10 KiB
C
452 lines
10 KiB
C
/*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <sata.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern void srio_init(void);
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#ifdef CONFIG_CPM2
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void config_8560_ioports (volatile ccsr_cpm_t * cpm)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (cpm, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_CPC
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static void enable_cpc(void)
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{
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int i;
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u32 size = 0;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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u32 cpccfg0 = in_be32(&cpc->cpccfg0);
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size += CPC_CFG0_SZ_K(cpccfg0);
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
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#endif
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out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
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/* Read back to sync write */
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in_be32(&cpc->cpccsr0);
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}
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printf("Corenet Platform Cache: %d KB enabled\n", size);
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}
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void invalidate_cpc(void)
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{
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int i;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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/* Flash invalidate the CPC and clear all the locks */
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out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
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while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
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;
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}
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}
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#else
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#define enable_cpc()
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#define invalidate_cpc()
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#endif /* CONFIG_SYS_FSL_CPC */
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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#ifdef CONFIG_FSL_CORENET
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static void corenet_tb_init(void)
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{
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volatile ccsr_rcpm_t *rcpm =
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(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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volatile ccsr_pic_t *pic =
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(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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u32 whoami = in_be32(&pic->whoami);
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/* Enable the timebase register for this core */
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out_be32(&rcpm->ctbenrl, (1 << whoami));
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}
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#endif
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void cpu_init_f (void)
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{
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extern void m8560_cpm_reset (void);
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#ifdef CONFIG_MPC8548
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ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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uint svr = get_svr();
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/*
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* CPU2 errata workaround: A core hang possible while executing
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* a msync instruction and a snoopable transaction from an I/O
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* master tagged to make quick forward progress is present.
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* Fixed in silicon rev 2.1.
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*/
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if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
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out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
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#endif
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disable_tlb(14);
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disable_tlb(15);
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#ifdef CONFIG_CPM2
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config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
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#endif
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init_early_memctl_regs();
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#if defined(CONFIG_CPM2)
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m8560_cpm_reset();
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#endif
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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#if defined(CONFIG_FSL_DMA)
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dma_init();
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#endif
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#ifdef CONFIG_FSL_CORENET
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corenet_tb_init();
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#endif
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init_used_tlb_cams();
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/* Invalidate the CPC before DDR gets enabled */
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invalidate_cpc();
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}
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/* Implement a dummy function for those platforms w/o SERDES */
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static void __fsl_serdes__init(void)
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{
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return ;
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}
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__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
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/*
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* Initialize L2 as cache.
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*
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* The newer 8548, etc, parts have twice as much cache, but
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* use the same bit-encoding as the older 8555, etc, parts.
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*
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_SYS_LBC_LCRR
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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flush_dcache();
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mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
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sync();
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#endif
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puts ("L2: ");
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#if defined(CONFIG_L2_CACHE)
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volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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volatile uint cache_ctl;
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uint svr, ver;
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uint l2srbar;
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u32 l2siz_field;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = l2cache->l2ctl;
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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if (cache_ctl & MPC85xx_L2CTL_L2E) {
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/* Clear L2 SRAM memory-mapped base address */
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out_be32(&l2cache->l2srbar0, 0x0);
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out_be32(&l2cache->l2srbar1, 0x0);
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/* set MBECCDIS=0, SBECCDIS=0 */
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clrbits_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC |
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MPC85xx_L2ERRDIS_SBECC));
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/* set L2E=0, L2SRAM=0 */
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clrbits_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E |
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MPC85xx_L2CTL_L2SRAM_ENTIRE));
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}
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#endif
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l2siz_field = (cache_ctl >> 28) & 0x3;
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switch (l2siz_field) {
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case 0x0:
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printf(" unknown size (0x%08x)\n", cache_ctl);
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return -1;
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break;
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case 0x1:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E) {
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puts("128 KB ");
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/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
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cache_ctl = 0xc4000000;
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} else {
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puts("256 KB ");
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cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
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}
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break;
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case 0x2:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E) {
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puts("256 KB ");
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/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
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cache_ctl = 0xc8000000;
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} else {
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puts ("512 KB ");
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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}
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break;
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case 0x3:
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puts("1024 KB ");
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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}
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if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
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puts("already enabled");
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l2srbar = l2cache->l2srbar0;
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#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
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if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
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&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
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l2srbar = CONFIG_SYS_INIT_L2_ADDR;
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l2cache->l2srbar0 = l2srbar;
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printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
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}
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#endif /* CONFIG_SYS_INIT_L2_ADDR */
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puts("\n");
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} else {
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asm("msync;isync");
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l2cache->l2ctl = cache_ctl; /* invalidate & enable */
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asm("msync;isync");
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puts("enabled\n");
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}
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#elif defined(CONFIG_BACKSIDE_L2_CACHE)
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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/* invalidate the L2 cache */
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mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
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while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
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;
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#ifdef CONFIG_SYS_CACHE_STASHING
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/* set stash id to (coreID) * 2 + 32 + L2 (1) */
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mtspr(SPRN_L2CSR1, (32 + 1));
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#endif
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/* enable the cache */
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mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
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if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
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while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
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;
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printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
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}
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#else
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puts("disabled\n");
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#endif
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enable_cpc();
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#ifdef CONFIG_QE
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uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
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qe_init(qe_base);
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qe_reset();
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#endif
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/* needs to be in ram since code uses global static vars */
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fsl_serdes_init();
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#ifdef CONFIG_SYS_SRIO
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srio_init();
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#endif
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#if defined(CONFIG_MP)
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setup_mp();
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
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{
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void *p;
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p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
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setbits_be32(p, 1 << (31 - 14));
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}
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#endif
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#ifdef CONFIG_SYS_LBC_LCRR
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/*
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* Modify the CLKDIV field of LCRR register to improve the writing
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* speed for NOR flash.
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*/
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clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
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__raw_readl(&lbc->lcrr);
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isync();
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#endif
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return 0;
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}
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extern void setup_ivors(void);
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void arch_preboot_os(void)
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{
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u32 msr;
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/*
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* We are changing interrupt offsets and are about to boot the OS so
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* we need to make sure we disable all async interrupts. EE is already
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* disabled by the time we get called.
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*/
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msr = mfmsr();
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msr &= ~(MSR_ME|MSR_CE|MSR_DE);
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mtmsr(msr);
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setup_ivors();
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}
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#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
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int sata_initialize(void)
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{
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if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
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return __sata_initialize();
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return 1;
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}
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#endif
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