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Haiying Wang dbbbb3abef Make DDR interleaving mode work correctly 
Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
 		2008-10-18 21:54:04 +02:00
..
Makefile FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00
common_timing_params.h FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00
ctrl_regs.c Make DDR interleaving mode work correctly 2008-10-18 21:54:04 +02:00
ddr.h rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
ddr1_2_dimm_params.h FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00
ddr1_dimm_params.c FSL DDR: Add DDR1 DIMM paramter support 2008-08-27 02:05:59 +02:00
ddr2_dimm_params.c FSL DDR: Add DDR2 DIMM paramter support 2008-08-27 02:06:00 +02:00
lc_common_dimm_params.c FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00
main.c Make DDR interleaving mode work correctly 2008-10-18 21:54:04 +02:00
options.c FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00
util.c FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 2008-08-27 02:05:58 +02:00