202 lines
5.2 KiB
C
202 lines
5.2 KiB
C
/*
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* Copyright (C) 2008 Atmel Corporation
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*
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* Configuration settings for the Favr-32 EarthLCD LCD kit.
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*
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/memory-map.h>
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#define CONFIG_AVR32 1
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#define CONFIG_AT32AP 1
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#define CONFIG_AT32AP7000 1
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#define CONFIG_FAVR32_EZKIT 1
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#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1
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/*
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* Timer clock frequency. We're using the CPU-internal COUNT register
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* for this, so this is equivalent to the CPU core clock frequency
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*/
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#define CFG_HZ 1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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* PLL frequency.
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* (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
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*/
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#define CONFIG_PLL 1
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#define CFG_POWER_MANAGER 1
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#define CFG_OSC0_HZ 20000000
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#define CFG_PLL0_DIV 1
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#define CFG_PLL0_MUL 7
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#define CFG_PLL0_SUPPRESS_CYCLES 16
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/*
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* Set the CPU running at:
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* PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
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*/
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#define CFG_CLKDIV_CPU 0
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/*
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* Set the HSB running at:
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* PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
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*/
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#define CFG_CLKDIV_HSB 1
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/*
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* Set the PBA running at:
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* PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
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*/
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#define CFG_CLKDIV_PBA 2
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/*
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* Set the PBB running at:
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* PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
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*/
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#define CFG_CLKDIV_PBB 1
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CFG_PLL0_OPT 0x04
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
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#define CONFIG_BOOTCOMMAND \
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"fsload; bootm $(fileaddr)"
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_AUTOBOOT 1
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* After booting the board for the first time, new ethernet addresses
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* should be generated and assigned to the environment variables
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* "ethaddr" and "eth1addr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
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#define CONFIG_NET_MULTI 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#undef CONFIG_CMD_AUTOSCRIPT
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_XIMG
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#define CONFIG_ATMEL_USART 1
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#define CONFIG_MACB 1
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#define CONFIG_PIO2 1
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#define CFG_NR_PIOS 5
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#define CFG_HSDRAMC 1
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#define CONFIG_MMC 1
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#define CONFIG_ATMEL_MCI 1
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#define CFG_DCACHE_LINESZ 32
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#define CFG_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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/* External flash on Favr-32 */
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#if 0
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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#endif
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#define CFG_FLASH_BASE 0x00000000
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#define CFG_FLASH_SIZE 0x800000
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 135
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CFG_SDRAM_BASE EBI_SDRAM_BASE
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 65536
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
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#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
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#define CFG_MALLOC_LEN (256*1024)
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#define CFG_DMA_ALLOC_LEN (16384)
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/* Allow 4MB for the kernel run-time image */
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#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CFG_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CFG_PROMPT "U-Boot> "
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#define CFG_CBSIZE 256
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#define CFG_MAXARGS 16
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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#define CFG_LONGHELP 1
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#define CFG_MEMTEST_START EBI_SDRAM_BASE
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#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
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#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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