phone-side
/
uboot-mt623x
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
uboot-mt623x/drivers/pci
History
Peter Tyser 009884ae35 pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOW 
When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as
they are found during bootup, eg:
  PCIE1: connected as Root Complex
        01:00.0 - 10b5:8518 - Bridge device
        02:01.0 - 10b5:8518 - Bridge device
        03:00.0 - 10b5:8112 - Bridge device
        04:01.0 - 8086:1010 - Network controller
        04:01.1 - 8086:1010 - Network controller
        02:02.0 - 10b5:8518 - Bridge device
        02:03.0 - 10b5:8518 - Bridge device
        06:00.0 - 10b5:8518 - Bridge device
        07:00.0 - 10b5:8518 - Bridge device
        08:00.0 - 1957:0040 - Processor
        07:01.0 - 10b5:8518 - Bridge device
        09:00.0 - 10b5:8112 - Bridge device
        07:02.0 - 10b5:8518 - Bridge device
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
        0d:00.0 - 1957:0040 - Processor
  PCIE2: Bus 0c - 0d

This information is useful, but its difficult to determine the PCI bus
topology.  To things clearer, we can use indention to make it more
obvious how the PCI bus is organized.  For the example above, the
updated output with this change is:

  PCIE1: connected as Root Complex
    01:00.0     - 10b5:8518 - Bridge device
     02:01.0    - 10b5:8518 - Bridge device
      03:00.0   - 10b5:8112 - Bridge device
       04:01.0  - 8086:1010 - Network controller
       04:01.1  - 8086:1010 - Network controller
     02:02.0    - 10b5:8518 - Bridge device
     02:03.0    - 10b5:8518 - Bridge device
      06:00.0   - 10b5:8518 - Bridge device
       07:00.0  - 10b5:8518 - Bridge device
        08:00.0 - 1957:0040 - Processor
       07:01.0  - 10b5:8518 - Bridge device
        09:00.0 - 10b5:8112 - Bridge device
       07:02.0  - 10b5:8518 - Bridge device
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
    0d:00.0     - 1957:0040 - Processor
  PCIE2: Bus 0c - 0d

In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch
(01:00 and 02:0x), which is connected to another PEX8518 PCIe switch
(06:00 and 07:0x), which then connects to a MPC8572 processor (08:00).
Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet
card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
 		2010-11-14 23:46:48 +01:00
..
Makefile ixp: move pci drivers to drivers/pci 2009-01-31 10:16:01 +01:00
fsl_pci_init.c fsl_pci_init: Quiet scanning printf() 2010-11-14 23:46:45 +01:00
pci.c pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOW 2010-11-14 23:46:48 +01:00
pci_auto.c Move arch/ppc to arch/powerpc 2010-04-21 23:42:38 +02:00
pci_indirect.c ppc4xx: Fix sending type 1 PCI transactions 2010-01-23 09:27:18 +01:00
pci_ixp.c pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity 2009-02-07 23:50:04 +01:00
pci_sh4.c sh: Move cpu/$CPU to arch/sh/cpu/$CPU 2010-04-13 09:13:17 +02:00
pci_sh7751.c sh: r2dplus fix register access 2008-12-10 23:11:36 +09:00
pci_sh7780.c sh: Add some register value configurable to PCI of SH7780 2009-03-12 23:58:30 +09:00
tsi108_pci.c pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity 2009-02-07 23:50:04 +01:00
w83c553f.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00