616 lines
18 KiB
ArmAsm
616 lines
18 KiB
ArmAsm
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This file is largely based on code obtned from AMD. AMD's original
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* copyright is included below
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*/
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/* TITLE SIZER - Aspen DRAM Sizing Routine.
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* =============================================================================
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*
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* Copyright 1999 Advanced Micro Devices, Inc.
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* You may redistribute this program and/or modify this program under the terms
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* of the GNU General Public License as published by the Free Software Foundation;
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* either version 2 of the License, or (at your option) any later version.
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*
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* This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
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* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
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* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
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* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
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* IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
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* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
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* INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
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* TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
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* LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
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* LIMITATION MAY NOT APPLY TO YOU.
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*
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* AMD does not assume any responsibility for any errors that may appear in
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* the Materials nor any responsibility to support or update the Materials.
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* AMD retains the right to make changes to its test specifications at any
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* time, without notice.
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* ==============================================================================
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*/
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/*
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******************************************************************************
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*
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* FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
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*
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*
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*
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* FUNCTIONS : sizemem() - jumped to, not called. To be executed after
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* reset to determine the size of the SDRAM DIMMs. Initializes
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* the memory subsystem.
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*
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*
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* AUTHOR : Buddy Fey - Original.
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*
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*
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* DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
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* NOTE: This is a small memory model version
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*
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*
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* INPUTS : BP contains return address offset
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* CACHE is assumed to be disabled.
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* The FS segment limit has already been set to big real mode
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* (full 32-bit addressing capability)
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*
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*
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* OUTPUTS : None
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*
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*
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* REG USE : ax,bx,cx,dx,di,si,bp, fs
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*
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*
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* REVISION : See PVCS info below
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*
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*
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* TEST PLAN CROSS REFERENCE:
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*
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*
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* $Workfile: $
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* $Revision: 1.2 $
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* $Date: 1999/09/22 12:49:33 $
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* $Author: chipf $
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* $Log: sizer.asm $
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* Revision 1.2 1999/09/22 12:49:33 chipf
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* Add legal header
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* FUNCTIONAL DESCRIPTION:
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* This routine is called to autodetect the geometry of the DRAM.
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*
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* This routine is called to determine the number of column bits for the DRAM
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* devices in this external bank. This routine assumes that the external bank
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* has been configured for an 11-bit column and for 4 internal banks. This gives
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* us the maximum address reach in memory. By writing a test value to the max
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* address and locating where it aliases to, we can determine the number of valid
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* column bits.
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*
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* This routine is called to determine the number of internal banks each DRAM
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* device has. The external bank (under test) is configured for maximum reach
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* with 11-bit columns and 4 internal banks. This routine will write to a max
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* address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
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* that column is a "don't care". If BA1 does not affect write/read of data,
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* then this device has only 2 internal banks.
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*
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* This routine is called to determine the ending address for this external
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* bank of SDRAM. We write to a max address with a data value and then disable
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* row address bits looking for "don't care" locations. Each "don't care" bit
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* represents a dividing of the maximum density (128M) by 2. By dividing the
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* maximum of 32 4M chunks in an external bank down by all the "don't care" bits
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* determined during sizing, we set the proper density.
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*
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* WARNINGS.
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* bp must be preserved because it is used for return linkage.
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*
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* EXIT
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* nothing returned - but the memory subsystem is enabled
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*******************************************************************************
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*/
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#include <config.h>
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.section .text
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.equ DRCCTL, 0x0fffef010 /* DRAM control register */
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.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
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.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
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.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
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.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
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.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
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.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
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.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
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.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
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.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
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.equ COL09_ADR, 0x0e000600 /* 9 col addrs */
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.equ COL08_ADR, 0x0e000200 /* 8 col addrs */
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.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
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.equ ROW13_ADR, 0x07000000 /* 13 row addrs */
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.equ ROW12_ADR, 0x03000000 /* 12 row addrs */
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.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
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.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
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.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
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.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
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.equ COL09_DATA, 0x09090909 /* 9 col data */
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.equ COL08_DATA, 0x08080808 /* 8 col data */
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.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
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.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
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.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
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.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
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.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
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.globl mem_init
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mem_init:
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/* Preserve Boot Flags */
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movl %ebx, %ebp
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/* initialize dram controller registers */
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xorw %ax, %ax
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movl $DBCTL, %edi
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movb %al, (%edi) /* disable write buffer */
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movl $ECCCTL, %edi
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movb %al, (%edi) /* disable ECC */
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movl $DRCTMCTL, %edi
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movb $0x1e, %al /* Set SDRAM timing for slowest */
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movb %al, (%edi)
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/* setup loop to do 4 external banks starting with bank 3 */
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movl $0xff000000, %eax /* enable last bank and setup */
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movl $DRCBENDADR, %edi /* ending address register */
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movl %eax, (%edi)
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movl $DRCCFG, %edi /* setup */
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movw $0xbbbb, %ax /* dram config register for */
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movw %ax, (%edi)
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/* issue a NOP to all DRAMs */
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movl $DRCCTL, %edi /* setup DRAM control register with */
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movb $0x01, %al /* Disable refresh,disable write buffer */
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movb %al, (%edi)
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movl $CACHELINESZ, %esi /* just a dummy address to write for */
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movw %ax, (%esi)
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/* delay for 100 usec? */
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movw $100, %cx
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sizdelay:
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loop sizdelay
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/* issue all banks precharge */
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movb $0x02, %al
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movb %al, (%edi)
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movw %ax, (%esi)
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/* issue 2 auto refreshes to all banks */
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movb $0x04, %al /* Auto refresh cmd */
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movb %al, (%edi)
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movw $0x02, %cx
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refresh1:
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movw %ax, (%esi)
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loop refresh1
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/* issue LOAD MODE REGISTER command */
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movb $0x03, %al /* Load mode register cmd */
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movb %al, (%edi)
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movw %ax, (%esi)
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/* issue 8 more auto refreshes to all banks */
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movb $0x04, %al /* Auto refresh cmd */
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movb %al, (%edi)
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movw $0x0008, %cx
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refresh2:
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movw %ax, (%esi)
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loop refresh2
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/* set control register to NORMAL mode */
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movb $0x00, %al /* Normal mode value */
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movb %al, (%edi)
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/*
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* size dram starting with external bank 3
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* moving to external bank 0
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*/
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movl $0x3, %ecx /* start with external bank 3 */
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nextbank:
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/* write col 11 wrap adr */
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movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
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movl %eax, (%esi) /* write max col pattern at max col adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write col 10 wrap adr */
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movl $COL10_ADR, %esi /* set address to 10 col wrap address */
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movl $COL10_DATA, %eax /* pattern for 10 col wrap */
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movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write col 9 wrap adr */
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movl $COL09_ADR, %esi /* set address to 9 col wrap address */
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movl $COL09_DATA, %eax /* pattern for 9 col wrap */
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movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write col 8 wrap adr */
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movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
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movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
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movl %eax, (%esi) /* write min col pattern @ min col adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write row 14 wrap adr */
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movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
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movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
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movl %eax, (%esi) /* write max row pattern at max row adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write row 13 wrap adr */
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movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
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movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
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movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write row 12 wrap adr */
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movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
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movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
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movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
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movl (%esi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/* write row 11 wrap adr */
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movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
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movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
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movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
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movl (%edi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* write row 10 wrap adr --- this write is really to determine
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* number of banks
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*/
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movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
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movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
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movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
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movl (%edi), %ebx /* optional read */
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cmpl %ebx, %eax /* to verify write */
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jnz bad_ram /* this ram is bad */
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/*
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* read data @ row 12 wrap adr to determine * banks,
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* and read data @ row 14 wrap adr to determine * rows.
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* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
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* if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
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* if data @ row 12 wrap == 11 or 12, we have 4 banks,
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*/
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xorw %di, %di /* value for 2 banks in DI */
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movl (%esi), %ebx /* read from 12 row wrap to check banks */
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/* (esi is setup from the write to row 12 wrap) */
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cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
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jz only2 /* if pattern == AA, we only have 2 banks */
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/* 4 banks */
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movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
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cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
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jz only2
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cmpl $ROW12_DATA, %ebx /* and 12 */
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jnz bad_ram /* its bad if not 11 or 12! */
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/* fall through */
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only2:
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/*
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* validate row mask
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*/
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movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
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movl (%esi), %eax /* read actual number of rows @ row14 adr */
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cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
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jb bad_ram
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cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
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ja bad_ram
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cmpb %ah, %al /* verify all 4 bytes of dword same */
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jnz bad_ram
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movl %eax, %ebx
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shrl $16, %ebx
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cmpw %bx, %ax
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jnz bad_ram
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/*
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* read col 11 wrap adr for real column data value
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*/
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movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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movl (%esi), %eax /* read real col number at max col adr */
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/*
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* validate column data
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*/
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cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
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jb bad_ram
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cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
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ja bad_ram
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subl $COL08_DATA, %eax /* normalize column data to zero */
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jc bad_ram
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cmpb %ah, %al /* verify all 4 bytes of dword equal */
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jnz bad_ram
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movl %eax, %edx
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shrl $16, %edx
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cmpw %dx, %ax
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jnz bad_ram
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/*
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* merge bank and col data together
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*/
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addw %di, %dx /* merge of bank and col info in dl */
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/*
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* fix ending addr mask based upon col info
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*/
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movb $0x03, %al
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subb %dh, %al /* dh contains the overflow from the bank/col merge */
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movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
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xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
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shrb %cl, %dh
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incb %dh /* ending addr is 1 greater than real end */
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xchgw %cx, %ax /* cx is bank number again */
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bad_reint:
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/*
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* issue all banks precharge
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*/
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movb $0x02, %al /* All banks precharge */
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movw %ax, (%esi)
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/*
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* update ENDING ADDRESS REGISTER
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*/
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movl %ecx, %ebx
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addl %ebx, %edi
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movb %dh, (%edi)
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/*
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* update CONFIG REGISTER
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*/
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xorb %dh, %dh
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movw $0x000f, %bx
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movw %cx, %ax
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shlw $2, %ax
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xchgw %cx, %ax
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shlw %cl, %dx
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shlw %cl, %bx
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notw %bx
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xchgw %cx, %ax
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movl $DRCCFG, %edi
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movw (%edi), %ax
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andw %bx, %ax
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orw %dx, %ax
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movw %ax, (%edi)
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jcxz cleanup
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decw %cx
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movl %ecx, %ebx
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movb $0xff, %al
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addl %ebx, %edi
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movb %al, (%edi)
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/*
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* set control register to NORMAL mode
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*/
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movb $0x00, %al /* Normal mode value */
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movw %ax, (%esi)
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jmp nextbank
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cleanup:
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movw $0x04, %cx
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xorw %ax, %ax
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cleanuplp:
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movb (%edi), %al
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orb %al, %al
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jz emptybank
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addb %ah, %al
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jns nottoomuch
|
|
|
|
movb $0x7f, %al
|
|
nottoomuch:
|
|
movb %al, %ah
|
|
orb $0x80, %al
|
|
movb %al, (%edi)
|
|
emptybank:
|
|
incl %edi
|
|
loop cleanuplp
|
|
|
|
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
|
|
/* just have your hardware desinger _GIVE_ you what you need here! */
|
|
movl $DRCTMCTL, %edi
|
|
movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
|
|
movb %al, (%edi)
|
|
#else
|
|
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
|
|
/*
|
|
* Set the CAS latency now since it is hard to do
|
|
* when we run from the RAM
|
|
*/
|
|
movl $DRCTMCTL, %edi /* DRAM timing register */
|
|
movb (%edi), %al
|
|
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
|
|
andb $0xef, %al
|
|
#endif
|
|
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
|
|
orb $0x10, %al
|
|
#endif
|
|
movb %al, (%edi)
|
|
#endif
|
|
#endif
|
|
movl $DRCCTL, %edi /* DRAM Control register */
|
|
movb $0x03, %al /* Load mode register cmd */
|
|
movb %al, (%edi)
|
|
movw %ax, (%esi)
|
|
|
|
|
|
movl $DRCCTL, %edi /* DRAM Control register */
|
|
movb $0x18, %al /* Enable refresh and NORMAL mode */
|
|
movb %al, (%edi)
|
|
|
|
jmp dram_done
|
|
|
|
bad_ram:
|
|
xorl %edx, %edx
|
|
xorl %edi, %edi
|
|
jmp bad_reint
|
|
|
|
dram_done:
|
|
/* Restore Boot Flags */
|
|
movl %ebx, %ebp
|
|
jmp mem_init_ret
|
|
|
|
#if CONFIG_SYS_SDRAM_ECC_ENABLE
|
|
.globl init_ecc
|
|
init_ecc:
|
|
/* A nominal memory test: just a byte at each address line */
|
|
movl %eax, %ecx
|
|
shrl $0x1, %ecx
|
|
movl $0x1, %edi
|
|
memtest0:
|
|
movb $0xa5, (%edi)
|
|
cmpb $0xa5, (%edi)
|
|
jne out
|
|
shrl $0x1, %ecx
|
|
andl %ecx, %ecx
|
|
jz set_ecc
|
|
shll $0x1, %edi
|
|
jmp memtest0
|
|
|
|
set_ecc:
|
|
/* clear all ram with a memset */
|
|
movl %eax, %ecx
|
|
xorl %esi, %esi
|
|
xorl %edi, %edi
|
|
xorl %eax, %eax
|
|
shrl $0x2, %ecx
|
|
cld
|
|
rep stosl
|
|
|
|
/* enable read, write buffers */
|
|
movb $0x11, %al
|
|
movl $DBCTL, %edi
|
|
movb %al, (%edi)
|
|
|
|
/* enable NMI mapping for ECC */
|
|
movl $ECCINT, %edi
|
|
movb $0x10, %al
|
|
movb %al, (%edi)
|
|
|
|
/* Turn on ECC */
|
|
movl $ECCCTL, %edi
|
|
movb $0x05, %al
|
|
movb %al,(%edi)
|
|
|
|
out:
|
|
jmp init_ecc_ret
|
|
#endif
|
|
|
|
/*
|
|
* Read and decode the sc520 DRCBENDADR MMCR and return the number of
|
|
* available ram bytes in %eax
|
|
*/
|
|
.globl get_mem_size
|
|
get_mem_size:
|
|
movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
|
bank0: movl (%edi), %eax
|
|
movl %eax, %ecx
|
|
andl $0x00000080, %ecx
|
|
jz bank1
|
|
andl $0x0000007f, %eax
|
|
shll $22, %eax
|
|
movl %eax, %edx
|
|
|
|
bank1: movl (%edi), %eax
|
|
movl %eax, %ecx
|
|
andl $0x00008000, %ecx
|
|
jz bank2
|
|
andl $0x00007f00, %eax
|
|
shll $14, %eax
|
|
movl %eax, %edx
|
|
|
|
bank2: movl (%edi), %eax
|
|
movl %eax, %ecx
|
|
andl $0x00800000, %ecx
|
|
jz bank3
|
|
andl $0x007f0000, %eax
|
|
shll $6, %eax
|
|
movl %eax, %edx
|
|
|
|
bank3: movl (%edi), %eax
|
|
movl %eax, %ecx
|
|
andl $0x80000000, %ecx
|
|
jz done
|
|
andl $0x7f000000, %eax
|
|
shrl $2, %eax
|
|
movl %eax, %edx
|
|
|
|
done:
|
|
movl %edx, %eax
|
|
jmp get_mem_size_ret
|