487 lines
11 KiB
C
487 lines
11 KiB
C
/*
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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mcftimer.h>
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#include <asm/timer.h>
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#include <asm/immap.h>
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#ifdef CONFIG_M5271
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#include <asm/m5271.h>
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#include <asm/immap_5271.h>
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#endif
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#ifdef CONFIG_M5272
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#include <asm/m5272.h>
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#include <asm/immap_5272.h>
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#endif
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#ifdef CONFIG_M5282
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#include <asm/m5282.h>
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#endif
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#ifdef CONFIG_M5249
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#include <asm/m5249.h>
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#include <asm/immap_5249.h>
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#endif
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static ulong timestamp;
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#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
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static unsigned short lastinc;
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#endif
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#if defined(CONFIG_M5272)
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/*
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* We use timer 3 which is running with a period of 1 us
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*/
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void udelay(unsigned long usec)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
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uint start, now, tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 3 as timebase clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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timerp->timer_tcn = 0;
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/* set period to 1 us */
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timerp->timer_tmr =
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(((CFG_CLK / 1000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
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MCFTIMER_TMR_ENABLE;
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start = now = timerp->timer_tcn;
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while (now < start + tmp)
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now = timerp->timer_tcn;
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}
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}
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void mcf_timer_interrupt(void *not_used)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
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volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
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/* check for timer 4 interrupts */
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if ((intp->int_isr & 0x01000000) != 0) {
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return;
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}
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/* reset timer */
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timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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timestamp++;
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}
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void timer_init(void)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
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volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
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timestamp = 0;
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/* Set up TIMER 4 as clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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/* initialize and enable timer 4 interrupt */
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irq_install_handler(72, mcf_timer_interrupt, 0);
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intp->int_icr1 |= 0x0000000d;
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timerp->timer_tcn = 0;
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timerp->timer_trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->timer_tmr =
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(((CFG_CLK / 1000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
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MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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}
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void reset_timer(void)
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{
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timestamp = 0;
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}
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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#endif
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#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
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void udelay(unsigned long usec)
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{
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volatile unsigned short *timerp;
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uint tmp;
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3);
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 3 as timebase clock */
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timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
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timerp[MCFTIMER_PMR] = 0;
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/* set period to 1 us */
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timerp[MCFTIMER_PCSR] =
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#ifdef CONFIG_M5271
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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timerp[MCFTIMER_PMR] = tmp;
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while (timerp[MCFTIMER_PCNTR] > 0) ;
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}
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}
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void timer_init(void)
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{
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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timestamp = 0;
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/* Set up TIMER 4 as poll clock */
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timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
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timerp[MCFTIMER_PMR] = lastinc = 0;
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timerp[MCFTIMER_PCSR] =
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#ifdef CONFIG_M5271
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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}
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void set_timer(ulong t)
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{
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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timestamp = 0;
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timerp[MCFTIMER_PMR] = lastinc = 0;
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}
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ulong get_timer(ulong base)
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{
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unsigned short now, diff;
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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now = timerp[MCFTIMER_PCNTR];
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diff = -(now - lastinc);
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timestamp += diff;
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lastinc = now;
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return timestamp - base;
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}
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void wait_ticks(unsigned long ticks)
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{
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set_timer(0);
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while (get_timer(0) < ticks) ;
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}
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#endif
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#if defined(CONFIG_M5249)
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/*
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* We use timer 1 which is running with a period of 1 us
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*/
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void udelay(unsigned long usec)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
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uint start, now, tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 1 as timebase clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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timerp->timer_tcn = 0;
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/* set period to 1 us */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr =
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(((CFG_CLK / 2000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
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MCFTIMER_TMR_ENABLE;
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start = now = timerp->timer_tcn;
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while (now < start + tmp)
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now = timerp->timer_tcn;
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}
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}
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void mcf_timer_interrupt(void *not_used)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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/* check for timer 2 interrupts */
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if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
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return;
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}
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/* reset timer */
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timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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timestamp++;
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}
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void timer_init(void)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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timestamp = 0;
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/* Set up TIMER 2 as clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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/* initialize and enable timer 2 interrupt */
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irq_install_handler(31, mcf_timer_interrupt, 0);
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mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
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mbar_writeByte(MCFSIM_TIMER2ICR,
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MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 |
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MCFSIM_ICR_PRI3);
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timerp->timer_tcn = 0;
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timerp->timer_trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr =
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(((CFG_CLK / 2000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
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MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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}
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void reset_timer(void)
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{
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timestamp = 0;
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}
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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#endif
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#if defined(CONFIG_MCFTMR)
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#ifndef CFG_UDELAY_BASE
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# error "uDelay base not defined!"
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#endif
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#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
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# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
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#endif
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extern void dtimer_intr_setup(void);
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void udelay(unsigned long usec)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE);
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uint start, now, tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 3 as timebase clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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timerp->tcn = 0;
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/* set period to 1 us */
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timerp->tmr =
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CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
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DTIM_DTMR_RST_EN;
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start = now = timerp->tcn;
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while (now < start + tmp)
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now = timerp->tcn;
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}
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}
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void dtimer_interrupt(void *not_used)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
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volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
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/* check for timer interrupt asserted */
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if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) {
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timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
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timestamp++;
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return;
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}
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}
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void timer_init(void)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
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timestamp = 0;
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timerp->tcn = 0;
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timerp->trr = 0;
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/* Set up TIMER 4 as clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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/* initialize and enable timer interrupt */
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irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
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timerp->tcn = 0;
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timerp->trr = 1000; /* Interrupt every ms */
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dtimer_intr_setup();
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
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DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
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}
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void reset_timer(void)
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{
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timestamp = 0;
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}
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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#endif /* CONFIG_MCFTMR */
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#if defined(CONFIG_MCFPIT)
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#if !defined(CFG_PIT_BASE)
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# error "CFG_PIT_BASE not defined!"
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#endif
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static unsigned short lastinc;
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void udelay(unsigned long usec)
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{
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volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE);
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uint tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 3 as timebase clock */
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timerp->pcsr = PIT_PCSR_OVW;
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timerp->pmr = 0;
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/* set period to 1 us */
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timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
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timerp->pmr = tmp;
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while (timerp->pcntr > 0) ;
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}
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}
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void timer_init(void)
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{
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volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
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timestamp = 0;
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/* Set up TIMER 4 as poll clock */
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timerp->pcsr = PIT_PCSR_OVW;
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timerp->pmr = lastinc = 0;
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timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
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}
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void set_timer(ulong t)
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{
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volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
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timestamp = 0;
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timerp->pmr = lastinc = 0;
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}
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ulong get_timer(ulong base)
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{
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unsigned short now, diff;
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volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
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now = timerp->pcntr;
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diff = -(now - lastinc);
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timestamp += diff;
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lastinc = now;
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return timestamp - base;
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}
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void wait_ticks(unsigned long ticks)
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{
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set_timer(0);
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while (get_timer(0) < ticks) ;
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}
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#endif /* CONFIG_MCFPIT */
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On M68K it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On M68K it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CFG_HZ;
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return tbclk;
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}
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