286 lines
6.2 KiB
C
286 lines
6.2 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <asm/mp.h>
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#include <netdev.h>
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#include <i2c.h>
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#include "../common/ngpixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(&gur->pmuxcr, 0x1000);
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/* Read back the register to synchronize the write. */
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in_be32(&gur->pmuxcr);
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/* Set the pin muxing to enable ETSEC2. */
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clrbits_be32(&gur->pmuxcr2, 0x001F8000);
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return 0;
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}
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int checkboard(void)
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{
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u8 sw;
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puts("Board: P1022DS ");
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
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sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
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switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
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case 0:
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printf ("vBank: %u\n", ((sw & 0x30) >> 4));
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break;
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case 1:
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printf ("NAND\n");
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break;
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case 2:
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case 3:
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puts ("Promjet\n");
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break;
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}
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#define CONFIG_TFP410_I2C_ADDR 0x38
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int misc_init_r(void)
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{
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u8 temp;
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/* Enable the TFP410 Encoder */
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temp = 0xBF;
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if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
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return -1;
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/* Verify if enabled */
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temp = 0;
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if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
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return -1;
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debug("DVI Encoder Read: 0x%02x\n", temp);
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temp = 0x10;
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if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
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return -1;
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/* Verify if enabled */
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temp = 0;
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if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
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return -1;
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debug("DVI Encoder Read: 0x%02x\n",temp);
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return 0;
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}
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static void configure_pcie(struct fsl_pci_info *info,
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struct pci_controller *hose,
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const char *connected)
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{
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static int bus_number = 0;
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int is_endpoint;
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set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
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set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
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is_endpoint = fsl_setup_hose(hose, info->regs);
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printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
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info->pci_num, connected,
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is_endpoint ? "Endpoint" : "Root Complex", info->regs);
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bus_number = fsl_pci_init_port(info, hose, bus_number);
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}
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_pci_info pci_info;
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u32 devdisr = in_be32(&gur->devdisr);
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#ifdef CONFIG_PCIE1
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if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
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SET_STD_PCIE_INFO(pci_info, 1);
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configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
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} else {
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printf(" PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
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SET_STD_PCIE_INFO(pci_info, 2);
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configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
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} else {
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printf(" PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCIE3
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if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
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SET_STD_PCIE_INFO(pci_info, 3);
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configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
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} else {
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printf(" PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
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#endif
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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return 0;
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}
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/*
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* Initialize on-board and/or PCI Ethernet devices
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*
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* Returns:
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* <0, error
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* 0, no ethernet devices found
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* >0, number of ethernet devices initialized
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*/
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int board_eth_init(bd_t *bis)
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{
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struct tsec_info_struct tsec_info[2];
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unsigned int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
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#else
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ft_fsl_pci_setup(blob, "pci0", NULL);
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#endif
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#ifdef CONFIG_PCIE2
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ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
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#else
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ft_fsl_pci_setup(blob, "pci1", NULL);
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#endif
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#ifdef CONFIG_PCIE3
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ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
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#else
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ft_fsl_pci_setup(blob, "pci2", NULL);
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#endif
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_fdt_fixup(blob);
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#endif
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}
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#endif
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#ifdef CONFIG_MP
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void board_lmb_reserve(struct lmb *lmb)
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{
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cpu_mp_lmb_reserve(lmb);
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}
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#endif
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