167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Author: Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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#define SRDS2_MAX_LANES 2
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {NONE, NONE, NONE, NONE},
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[0x01] = {NONE, NONE, NONE, NONE},
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[0x02] = {NONE, NONE, NONE, NONE},
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[0x03] = {NONE, NONE, NONE, NONE},
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[0x04] = {NONE, NONE, NONE, NONE},
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[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x09] = {PCIE1, NONE, NONE, NONE},
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[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
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};
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static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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[0x00] = {PCIE3, PCIE3},
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[0x01] = {PCIE2, PCIE3},
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[0x02] = {SATA1, SATA2},
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[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x04] = {NONE, NONE},
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[0x06] = {SATA1, SATA2},
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[0x07] = {NONE, NONE},
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[0x09] = {PCIE3, PCIE2},
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[0x0a] = {SATA1, SATA2},
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[0x0b] = {NONE, NONE},
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[0x0d] = {PCIE3, PCIE2},
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[0x0e] = {SATA1, SATA2},
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[0x0f] = {NONE, NONE},
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[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x16] = {SATA1, SATA2},
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[0x17] = {NONE, NONE},
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[0x18] = {PCIE3, PCIE3},
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[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1a] = {SATA1, SATA2},
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[0x1b] = {NONE, NONE},
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[0x1c] = {PCIE3, PCIE3},
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[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1e] = {SATA1, SATA2},
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[0x1f] = {NONE, NONE},
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};
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/*
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* A list of PCI and SATA slots
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*/
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enum slot_id {
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SLOT_PCIE1 = 1,
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SLOT_PCIE2,
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SLOT_PCIE3,
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SLOT_PCIE4,
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SLOT_PCIE5,
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SLOT_SATA1,
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SLOT_SATA2
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};
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/*
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* This array maps the slot identifiers to their names on the P1022DS board.
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*/
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static const char *slot_names[] = {
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[SLOT_PCIE1] = "Slot 1",
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[SLOT_PCIE2] = "Slot 2",
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[SLOT_PCIE3] = "Slot 3",
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[SLOT_PCIE4] = "Slot 4",
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[SLOT_PCIE5] = "Mini-PCIe",
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[SLOT_SATA1] = "SATA 1",
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[SLOT_SATA2] = "SATA 2",
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};
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/*
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* This array maps a given SERDES configuration and SERDES device to the PCI or
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* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
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*/
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static u8 serdes_dev_slot[][SATA2 + 1] = {
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[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
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[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
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[PCIE2] = SLOT_PCIE5 },
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[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3 },
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[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1c] = { [PCIE1] = SLOT_PCIE1,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
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[0x1f] = { [PCIE1] = SLOT_PCIE1 },
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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unsigned int i;
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debug("%s: dev = %d\n", __FUNCTION__, device);
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debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
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return 0;
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}
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for (i = 0; i < SRDS1_MAX_LANES; i++) {
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if (serdes1_cfg_tbl[srds_cfg][i] == device)
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return 1;
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if (serdes2_cfg_tbl[srds_cfg][i] == device)
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return 1;
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}
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return 0;
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}
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/*
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* Returns the name of the slot to which the PCIe or SATA controller is
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* connected
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*/
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const char *serdes_slot_name(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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enum slot_id slot = serdes_dev_slot[srds_cfg][device];
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const char *name = slot_names[slot];
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if (name)
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return name;
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else
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return "Nothing";
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}
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