254 lines
6.3 KiB
C
254 lines
6.3 KiB
C
/*
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* GNU General Public License for more details.
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*
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* MATRIX Vision GmbH / June 2002-Nov 2003
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* Andre Schwarz
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#endif
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u32 get_BoardType(void);
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#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
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| ((d&0x1f)<<11) \
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| ((f&0x7)<<7) \
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| (r&0xfc) )
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int mv_pci_read( int bus, int dev, int func, int reg )
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{
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*(u32*)(0xfec00cf8) = PCI_CONFIG(bus,dev,func,reg);
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asm("sync");
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return cpu_to_le32( *(u32*)(0xfee00cfc) );
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}
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u32 get_BoardType() {
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return ( mv_pci_read(0,0xe,0,0) == 0x06801095 ? 0 : 1 );
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}
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void init_2nd_DUART(void)
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{
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NS16550_t console = (NS16550_t)CFG_NS16550_COM2;
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int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
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*(u8*)(0xfc004511) = 0x1;
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NS16550_init(console, clock_divisor);
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}
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void hw_watchdog_reset(void)
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{
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if (get_BoardType() == 0 ) {
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*(u32*)(0xff000005) = 0;
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asm("sync");
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}
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}
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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ulong busfreq = get_bus_freq(0);
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char buf[32];
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u32 BoardType = get_BoardType();
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char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
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char *p;
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bd_t *bd = gd->bd;
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hw_watchdog_reset();
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printf("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
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printf(" Found %s running at %s MHz memory clock.\n", BoardName[BoardType], strmhz(buf, busfreq) );
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init_2nd_DUART();
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if ( (p = getenv("console_nr")) != NULL ) {
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unsigned long con_nr = simple_strtoul( p, NULL, 10) & 3;
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bd->bi_baudrate &= ~3;
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bd->bi_baudrate |= con_nr & 3;
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}
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return 0;
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}
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long int initdram (int board_type)
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{
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int i, cnt;
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volatile uchar * base= CFG_SDRAM_BASE;
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volatile ulong * addr;
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ulong save[32];
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ulong val, ret = 0;
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for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = (volatile ulong *)base + cnt;
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save[i++] = *addr;
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*addr = ~cnt;
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}
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addr = (volatile ulong *)base;
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save[i] = *addr;
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*addr = 0;
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if (*addr != 0) {
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*addr = save[i];
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goto Done;
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}
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for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
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addr = (volatile ulong *)base + cnt;
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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ulong new_bank0_end = cnt * sizeof(long) - 1;
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ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
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ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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ret = cnt * sizeof(long);
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goto Done;
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}
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}
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ret = CFG_MAX_RAM_SIZE;
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Done:
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return ret;
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}
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/* ------------------------------------------------------------------------- */
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u8 *dhcp_vendorex_prep(u8 *e)
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{
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char *ptr;
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/* DHCP vendor-class-identifier = 60 */
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if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
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*e++ = 60;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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/* my DHCP_CLIENT_IDENTIFIER = 61 */
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if ((ptr = getenv("dhcp_client_id"))) {
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*e++ = 61;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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return e;
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}
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u8 *dhcp_vendorex_proc(u8 *popt)
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{
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return NULL;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Initialize PCI Devices
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*/
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#ifdef CONFIG_PCI
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void pci_mvblue_clear_base( struct pci_controller *hose, pci_dev_t dev )
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{
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u32 cnt;
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printf("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV(dev), PCI_FUNC(dev) );
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for( cnt = 0; cnt < 6; cnt++ )
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pci_hose_write_config_dword( hose, dev, 0x10 + (4*cnt), 0x0 );
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printf("done\n");
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}
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void duart_setup( u32 base, u16 divisor )
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{
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printf("duart setup ...");
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out_8( (u8*)( CFG_ISA_IO+base+3), 0x80);
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out_8( (u8*)( CFG_ISA_IO+base+0), divisor & 0xff);
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out_8( (u8*)( CFG_ISA_IO+base+1), divisor >> 8 );
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out_8( (u8*)( CFG_ISA_IO+base+3), 0x03);
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out_8( (u8*)( CFG_ISA_IO+base+4), 0x03);
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out_8( (u8*)( CFG_ISA_IO+base+2), 0x07);
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printf("done\n");
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}
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void pci_mvblue_fixup_irq_behind_bridge( struct pci_controller *hose, pci_dev_t bridge, unsigned char irq)
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{
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pci_dev_t d;
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unsigned char bus;
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unsigned short vendor,
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class;
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pci_hose_read_config_byte( hose, bridge, PCI_SECONDARY_BUS, &bus );
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for (d = PCI_BDF(bus,0,0);
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d < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
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d += PCI_BDF(0,0,1))
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{
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pci_hose_read_config_word(hose, d, PCI_VENDOR_ID, &vendor);
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if (vendor != 0xffff && vendor != 0x0000)
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{
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pci_hose_read_config_word( hose, d, PCI_CLASS_DEVICE, &class );
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if ( class == PCI_CLASS_BRIDGE_PCI )
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pci_mvblue_fixup_irq_behind_bridge( hose, d, irq );
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else
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pci_hose_write_config_byte( hose, d, PCI_INTERRUPT_LINE, irq );
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}
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}
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}
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#define MV_MAX_PCI_BUSSES 3
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#define SLOT0_IRQ 3
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#define SLOT1_IRQ 4
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void pci_mvblue_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char line=0xff;
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unsigned short class;
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if( PCI_BUS(dev) == 0 ) {
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switch(PCI_DEV(dev)) {
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case 0xd:
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if ( get_BoardType() == 0 ) {
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line = 1;
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} else
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/* mvBL */
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line = 2;
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break;
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case 0xe:
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/* mvBB: IDE */
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line = 2;
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pci_hose_write_config_byte(hose, dev, 0x8a, 0x20 );
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break;
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case 0xf:
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/* mvBB: Slot0 (Grabber) */
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pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
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if ( class == PCI_CLASS_BRIDGE_PCI ) {
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pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT0_IRQ );
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line = 0xff;
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} else
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line = SLOT0_IRQ;
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break;
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case 0x10:
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/* mvBB: Slot1 */
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pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
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if ( class == PCI_CLASS_BRIDGE_PCI ) {
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pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT1_IRQ );
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line = 0xff;
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} else
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line = SLOT1_IRQ;
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break;
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default:
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printf("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV(dev) );
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line = 0xff;
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break;
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}
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line );
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}
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}
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struct pci_controller hose = {
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fixup_irq: pci_mvblue_fixup_irq
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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#endif
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