295 lines
6.9 KiB
C
295 lines
6.9 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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enum pll_clocks {
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PLL1_CLOCK = 0,
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PLL2_CLOCK,
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PLL3_CLOCK,
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PLL_CLOCKS,
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};
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struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
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[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
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[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
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[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
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};
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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/*
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* Calculate the frequency of this pll.
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*/
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static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
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{
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u32 mfi, mfn, mfd, pd;
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mfn = __raw_readl(&pll->mfn);
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mfd = __raw_readl(&pll->mfd) + 1;
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mfi = __raw_readl(&pll->op);
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pd = (mfi & 0xF) + 1;
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mfi = (mfi >> 4) & 0xF;
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mfi = (mfi >= 5) ? mfi : 5;
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return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
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}
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/*
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* Get mcu main rate
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*/
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u32 get_mcu_main_clk(void)
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{
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u32 reg, freq;
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reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
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MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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return freq / (reg + 1);
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}
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/*
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* Get the rate of peripheral's root clock.
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*/
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static u32 get_periph_clk(void)
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{
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u32 reg;
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reg = __raw_readl(&mxc_ccm->cbcdr);
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if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
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reg = __raw_readl(&mxc_ccm->cbcmr);
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switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
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MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
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case 0:
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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case 1:
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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default:
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return 0;
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}
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/* NOTREACHED */
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}
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/*
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* Get the rate of ipg clock.
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*/
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static u32 get_ipg_clk(void)
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{
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u32 ahb_podf, ipg_podf;
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ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
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ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
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MXC_CCM_CBCDR_IPG_PODF_OFFSET;
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ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
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MXC_CCM_CBCDR_AHB_PODF_OFFSET;
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return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
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}
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/*
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* Get the rate of ipg_per clock.
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*/
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static u32 get_ipg_per_clk(void)
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{
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u32 pred1, pred2, podf;
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if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
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return get_ipg_clk();
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/* Fixme: not handle what about lpm*/
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podf = __raw_readl(&mxc_ccm->cbcdr);
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pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
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pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
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podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
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return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
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}
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/*
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* Get the rate of uart clk.
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*/
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static u32 get_uart_clk(void)
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{
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unsigned int freq, reg, pred, podf;
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reg = __raw_readl(&mxc_ccm->cscmr1);
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switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
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MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
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case 0x0:
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freq = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x1:
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freq = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x2:
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freq = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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default:
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return 66500000;
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}
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reg = __raw_readl(&mxc_ccm->cscdr1);
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pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
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MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
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podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
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MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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freq /= (pred + 1) * (podf + 1);
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return freq;
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}
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/*
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* This function returns the low power audio clock.
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*/
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u32 get_lp_apm(void)
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{
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u32 ret_val = 0;
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u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
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if (((ccsr >> 9) & 1) == 0)
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ret_val = CONFIG_SYS_MX5_HCLK;
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else
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ret_val = ((32768 * 1024));
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return ret_val;
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}
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/*
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* get cspi clock rate.
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*/
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u32 imx_get_cspiclk(void)
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{
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u32 ret_val = 0, pdf, pre_pdf, clk_sel;
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u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
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u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
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pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
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>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
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pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
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>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
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clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
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>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
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switch (clk_sel) {
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case 0:
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ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 1:
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ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 2:
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ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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default:
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ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
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break;
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}
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return ret_val;
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}
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/*
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* The API of get mxc clockes.
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*/
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_AHB_CLK:
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break;
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_IPG_PERCLK:
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return get_ipg_per_clk();
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case MXC_UART_CLK:
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return get_uart_clk();
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case MXC_CSPI_CLK:
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return imx_get_cspiclk();
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case MXC_FEC_CLK:
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return decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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default:
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break;
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}
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return -1;
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}
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u32 imx_get_uartclk(void)
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{
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return get_uart_clk();
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}
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u32 imx_get_fecclk(void)
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{
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return mxc_get_clock(MXC_IPG_CLK);
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}
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/*
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* Dump some core clockes.
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*/
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int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u32 freq;
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll1: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll2: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll3: %dMHz\n", freq / 1000000);
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printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
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printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
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return 0;
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}
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/***************************************************/
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U_BOOT_CMD(
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clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
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"display clocks\n",
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""
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);
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