120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/*
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* (C) 2010 by Tieto <www.tieto.com>
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* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-mtk/emi.h>
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#include <asm/arch-mtk/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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void show_boot_progress(int progress)
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{
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printf("%i\n", progress);
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_SCIPHONE_G2;
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gd->bd->bi_boot_params = 0x00000100;
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/* Powerup BB */
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writew(POWERKEY1_MAGIC, MTK_RTC_POWERKEY1);
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writew(POWERKEY2_MAGIC, MTK_RTC_POWERKEY2);
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writew(BBPU_MAGIC | RTC_BBPU_WRITE_EN |
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RTC_BBPU_BBPU | RTC_BBPU_AUTO,
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MTK_RTC_BBPU);
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writew(1, MTK_RTC_WRTGR);
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/* Disable watchdog */
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writew(WDT_MODE_KEY, MTK_RGU_WDT_MODE);
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writew(WDT_MODE_KEY, MTK_RGU_WDT_MODE);
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/*
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* PLL configuration influents JTAG clock.
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* Currently it's disabled to avoid problems with JTAG.
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*/
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#if 0
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/* Power on PLL */
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writew(0, MTK_PLL_PDN_CON);
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/* Turn on MCU and DSP dividers, mark that SYSCLK is 26MHz */
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writew(PLL_CLKSQ_DIV2_DSP | PLL_CLKSQ_DIV2_MCU | PLL_SRCCLK,
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MTK_PLL_CLK_CON);
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/* Reset PLL */
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writew(PLL_RST, MTK_PLL_PLL);
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writew(0, MTK_PLL_PLL);
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udelay(100);
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/* Turn on PLL for MCU, DSP and USB */
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writew(PLL_MPLLSEL_PLL | PLL_DPLLSEL | PLL_UPLLSEL, MTK_PLL_PLL);
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/*
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* Setup MCU clock register:
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* ARMCLK = 208MHz, AHBx4CLK = 52MHz, AHBx8CLK = 104MHz
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* we have to write to the read-only part (EMICLK) as well, otherwise
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* the EMI won't work! (datasheet lies)
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*/
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writew(7 << MCUCLK_CON_AHBX8CLK_SHIFT |
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3 << MCUCLK_CON_AHBX4CLK_SHIFT |
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15 << MCUCLK_CON_ARMCLK_SHIFT |
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7 << MCUCLK_CON_EMICLK_SHIFT,
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MTK_CONFG_MCUCLK_CON);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(PHYS_SDRAM_1, CONFIG_MAX_RAM_BANK_SIZE);
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/*
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* Currently UBoot is executed from external RAM and below configuration
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* will make it to stop working. This code will be uncommented when
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* UBoot will be placed in NAND memory.
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*/
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#if 0
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/* Configure DRAM controller */
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writel(0x0001000E, MTK_EMI_GEND);
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writel(0x00088E3A, MTK_EMI_GENA);
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writel(0x000000C0, MTK_EMI_GENB);
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writel(0x18C618C6, MTK_EMI_GENC);
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writel(0x18007505, MTK_EMI_CONL);
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writel(0x00002828, MTK_EMI_CONM);
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writel(0x00332000, MTK_EMI_CONI);
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writel(0x3CD24431, MTK_EMI_CONJ);
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writel(0x02000000, MTK_EMI_CONK);
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for (i = 0; i < 5; ++i) {
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/* Setup five single bits, one by one for DRAM init */
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writel((1 << (24 + i)) | (0x500013), MTK_EMI_CONN);
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udelay(1);
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writel(0x500013, MTK_EMI_CONN);
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udelay(1);
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}
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#endif
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return 0;
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}
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