Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration ... For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>		2009-01-23 17:03:14 -06:00
..
Makefile	FSL DDR: Convert MPC8544DS to new DDR code.	2008-08-27 11:43:50 -05:00
config.mk	Add MPC8544DS basic port board files.	2007-04-23 19:58:28 -05:00
ddr.c	fsl-ddr: use the 1T timing as default configuration	2009-01-23 17:03:14 -06:00
law.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
mpc8544ds.c	85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards	2009-01-23 17:03:13 -06:00
tlb.c	85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards	2009-01-23 17:03:13 -06:00
u-boot.lds	mpc85xx: workaround old binutils bug	2008-08-10 22:41:12 +02:00