570 lines
19 KiB
C
570 lines
19 KiB
C
/****************************************************************************
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*
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* BIOS emulator and interface
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* to Realmode X86 Emulator Library
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*
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* Copyright (C) 1996-1999 SciTech Software, Inc.
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*
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* ========================================================================
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*
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* Permission to use, copy, modify, distribute, and sell this software and
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* its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of the authors not be used
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* in advertising or publicity pertaining to distribution of the software
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* without specific, written prior permission. The authors makes no
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* representations about the suitability of this software for any purpose.
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* It is provided "as is" without express or implied warranty.
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*
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* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
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* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*
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* ========================================================================
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*
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* Language: ANSI C
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* Environment: Any
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* Developer: Kendall Bennett
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*
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* Description: Module to implement warm booting of all PCI/AGP controllers
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* on the bus. We use the x86 real mode emulator to run the
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* BIOS on the primary and secondary controllers to bring
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* the cards up.
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*
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****************************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdarg.h>
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#include "biosemu.h"
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#ifndef _MAX_PATH
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#define _MAX_PATH 256
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#endif
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/*------------------------- Global Variables ------------------------------*/
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static PCIDeviceInfo PCI[MAX_PCI_DEVICES];
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static int NumPCI = -1;
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static int BridgeIndex[MAX_PCI_DEVICES] = {0};
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static int NumBridges;
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static PCIBridgeInfo *AGPBridge = NULL;
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static int DeviceIndex[MAX_PCI_DEVICES] = {0};
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static int NumDevices;
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static u32 debugFlags = 0;
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static BE_VGAInfo VGAInfo[MAX_PCI_DEVICES] = {{0}};
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static ibool useV86 = false;
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static ibool forcePost = false;
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/* Length of the BIOS image */
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#define MAX_BIOSLEN (64 * 1024L)
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#define FINAL_BIOSLEN (32 * 1024L)
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/* Macro to determine if the VGA is enabled and responding */
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#define VGA_NOT_ACTIVE() (forcePost || (PM_inpb(0x3CC) == 0xFF) || ((PM_inpb(0x3CC) & 0x2) == 0))
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#define ENABLE_DEVICE(device) \
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PCI_writePCIRegB(0x4,PCI[DeviceIndex[device]].Command | 0x7,device)
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#define DISABLE_DEVICE(device) \
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PCI_writePCIRegB(0x4,0,device)
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/* Macros to enable and disable AGP VGA resources */
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#define ENABLE_AGP_VGA() \
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PCI_accessReg(0x3E,AGPBridge->BridgeControl | 0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
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#define DISABLE_AGP_VGA() \
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PCI_accessReg(0x3E,AGPBridge->BridgeControl & ~0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
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#define RESTORE_AGP_VGA() \
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PCI_accessReg(0x3E,AGPBridge->BridgeControl,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
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/*-------------------------- Implementation -------------------------------*/
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/****************************************************************************
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RETURNS:
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The address to use to map the secondary BIOS (PCI/AGP devices)
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REMARKS:
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Searches all the PCI base address registers for the device looking for a
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memory mapping that is large enough to hold our ROM BIOS. We usually end up
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finding the framebuffer mapping (usually BAR 0x10), and we use this mapping
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to map the BIOS for the device into. We use a mapping that is already
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assigned to the device to ensure the memory range will be passed through
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by any PCI->PCI or AGP->PCI bridge that may be present.
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NOTE: Usually this function is only used for AGP devices, but it may be
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used for PCI devices that have already been POST'ed and the BIOS
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ROM base address has been zero'ed out.
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****************************************************************************/
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static ulong PCI_findBIOSAddr(
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int device)
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{
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ulong base,size;
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int bar;
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for (bar = 0x10; bar <= 0x14; bar++) {
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base = PCI_readPCIRegL(bar,device) & ~0xFF;
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if (!(base & 0x1)) {
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PCI_writePCIRegL(bar,0xFFFFFFFF,device);
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size = PCI_readPCIRegL(bar,device) & ~0xFF;
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size = ~size+1;
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PCI_writePCIRegL(bar,0,device);
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if (size >= MAX_BIOSLEN)
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return base;
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}
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}
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return 0;
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}
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/****************************************************************************
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REMARKS:
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Re-writes the PCI base address registers for the secondary PCI controller
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with the values from our initial PCI bus enumeration. This fixes up the
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values after we have POST'ed the secondary display controller BIOS, which
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may have incorrectly re-programmed the base registers the same as the
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primary display controller (the case for identical S3 cards).
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****************************************************************************/
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static void _PCI_fixupSecondaryBARs(void)
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{
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int i;
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for (i = 0; i < NumDevices; i++) {
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PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i);
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PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i);
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PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i);
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PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i);
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PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i);
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PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i);
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}
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}
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/****************************************************************************
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RETURNS:
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True if successfully initialised, false if not.
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REMARKS:
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This function executes the BIOS POST code on the controller. We assume that
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at this stage the controller has its I/O and memory space enabled and
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that all other controllers are in a disabled state.
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****************************************************************************/
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static void PCI_doBIOSPOST(
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int device,
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ulong BIOSPhysAddr,
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void *mappedBIOS,
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ulong BIOSLen)
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{
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RMREGS regs;
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RMSREGS sregs;
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/* Determine the value to store in AX for BIOS POST */
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regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8);
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if (useV86) {
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/* Post the BIOS using the PM functions (ie: v86 mode on Linux) */
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if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) {
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/* If the PM function fails, this probably means are we are on */
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/* DOS and can't re-map the real mode 0xC0000 region. In thise */
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/* case if the device is the primary, we can use the real */
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/* BIOS at 0xC0000 directly. */
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if (device == 0)
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PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen);
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}
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}
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else {
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/* Setup the X86 emulator for the VGA BIOS */
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BE_setVGA(&VGAInfo[device]);
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/* Execute the BIOS POST code */
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BE_callRealMode(0xC000,0x0003,®s,&sregs);
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/* Cleanup and exit */
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BE_getVGA(&VGAInfo[device]);
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}
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}
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/****************************************************************************
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RETURNS:
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True if successfully initialised, false if not.
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REMARKS:
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Loads and POST's the secondary controllers BIOS, directly from the BIOS
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image we can extract over the PCI bus.
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****************************************************************************/
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static ibool PCI_postControllers(void)
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{
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int device;
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ulong BIOSImageLen,mappedBIOSPhys;
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uchar *mappedBIOS,*copyOfBIOS;
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char filename[_MAX_PATH];
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FILE *f;
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/* Disable the primary display controller and AGP VGA pass-through */
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DISABLE_DEVICE(0);
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if (AGPBridge)
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DISABLE_AGP_VGA();
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/* Now POST all the secondary controllers */
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for (device = 0; device < NumDevices; device++) {
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/* Skip the device if it is not enabled (probably an ISA device) */
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if (DeviceIndex[device] == -1)
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continue;
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/* Enable secondary display controller. If the secondary controller */
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/* is on the AGP bus, then enable VGA resources for the AGP device. */
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ENABLE_DEVICE(device);
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if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus)
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ENABLE_AGP_VGA();
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/* Check if the controller has already been POST'ed */
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if (VGA_NOT_ACTIVE()) {
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/* Find a viable place to map the secondary PCI BIOS image and map it */
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printk("Device %d not enabled, so attempting warm boot it\n", device);
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/* For AGP devices (and PCI devices that do have the ROM base */
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/* address zero'ed out) we have to map the BIOS to a location */
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/* that is passed by the AGP bridge to the bus. Some AGP devices */
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/* have the ROM base address already set up for us, and some */
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/* do not (we map to one of the existing BAR locations in */
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/* this case). */
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mappedBIOS = NULL;
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if (PCI[DeviceIndex[device]].ROMBaseAddress != 0)
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mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF;
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else
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mappedBIOSPhys = PCI_findBIOSAddr(device);
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printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys);
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mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false);
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PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device);
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BIOSImageLen = mappedBIOS[2] * 512;
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if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL)
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return false;
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memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen);
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PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1);
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/* Allocate memory to store copy of BIOS from secondary controllers */
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VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]];
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VGAInfo[device].BIOSImage = copyOfBIOS;
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VGAInfo[device].BIOSImageLen = BIOSImageLen;
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/* Restore device mappings */
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PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device);
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PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device);
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PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device);
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/* Now execute the BIOS POST for the device */
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if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) {
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printk("Executing BIOS POST for controller.\n");
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PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen);
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}
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/* Reset the size of the BIOS image to the final size */
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VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN;
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/* Save the BIOS and interrupt vector information to disk */
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sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device);
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if ((f = fopen(filename,"wb")) != NULL) {
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fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f);
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fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f);
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fclose(f);
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}
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}
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else {
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/* Allocate memory to store copy of BIOS from secondary controllers */
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if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL)
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return false;
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VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]];
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VGAInfo[device].BIOSImage = copyOfBIOS;
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VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN;
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/* Load the BIOS and interrupt vector information from disk */
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sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device);
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if ((f = fopen(filename,"rb")) != NULL) {
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fread(copyOfBIOS,1,FINAL_BIOSLEN,f);
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fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f);
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fclose(f);
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}
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}
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/* Fix up all the secondary PCI base address registers */
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/* (restores them all from the values we read previously) */
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_PCI_fixupSecondaryBARs();
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/* Disable the secondary controller and AGP VGA pass-through */
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DISABLE_DEVICE(device);
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if (AGPBridge)
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DISABLE_AGP_VGA();
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}
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/* Reenable primary display controller and reset AGP bridge control */
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if (AGPBridge)
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RESTORE_AGP_VGA();
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ENABLE_DEVICE(0);
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/* Free physical BIOS image mapping */
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PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1);
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/* Restore the X86 emulator BIOS info to primary controller */
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if (!useV86)
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BE_setVGA(&VGAInfo[0]);
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return true;
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}
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/****************************************************************************
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REMARKS:
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Enumerates the PCI bus and dumps the PCI configuration information to the
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log file.
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****************************************************************************/
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static void EnumeratePCI(void)
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{
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int i,index;
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PCIBridgeInfo *info;
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printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n",
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NumPCI, NumDevices);
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for (index = 0; index < NumDevices; index++)
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printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]);
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printk("\n");
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printk("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n");
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for (i = 0; i < NumPCI; i++) {
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printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ",
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PCI[i].slot.p.Bus,
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PCI[i].slot.p.Device,
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PCI[i].slot.p.Function,
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PCI[i].VendorID,
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PCI[i].DeviceID,
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PCI[i].SubSystemVendorID,
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PCI[i].SubSystemID,
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PCI[i].RevID,
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PCI[i].BaseClass,
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PCI[i].SubClass,
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PCI[i].InterruptLine,
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PCI[i].InterruptPin,
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PCI[i].Command);
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for (index = 0; index < NumDevices; index++) {
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if (DeviceIndex[index] == i)
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break;
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}
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if (index < NumDevices)
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printk("<- %d\n", index);
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else
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printk("\n");
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}
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printk("\n");
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printk("DeviceID Stat Ifc Cch Lat Hdr BIST\n");
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for (i = 0; i < NumPCI; i++) {
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printk("%04X:%04X %04X %02X %02X %02X %02X %02X ",
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PCI[i].VendorID,
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PCI[i].DeviceID,
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PCI[i].Status,
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PCI[i].Interface,
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PCI[i].CacheLineSize,
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PCI[i].LatencyTimer,
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PCI[i].HeaderType,
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PCI[i].BIST);
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for (index = 0; index < NumDevices; index++) {
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if (DeviceIndex[index] == i)
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break;
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}
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if (index < NumDevices)
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printk("<- %d\n", index);
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else
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printk("\n");
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}
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printk("\n");
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printk("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n");
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for (i = 0; i < NumPCI; i++) {
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printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ",
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PCI[i].VendorID,
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PCI[i].DeviceID,
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PCI[i].BaseAddress10,
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PCI[i].BaseAddress14,
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PCI[i].BaseAddress18,
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PCI[i].BaseAddress1C,
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PCI[i].BaseAddress20,
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PCI[i].BaseAddress24,
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PCI[i].ROMBaseAddress);
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for (index = 0; index < NumDevices; index++) {
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if (DeviceIndex[index] == i)
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break;
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}
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if (index < NumDevices)
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printk("<- %d\n", index);
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else
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printk("\n");
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}
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printk("\n");
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printk("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n");
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for (i = 0; i < NumPCI; i++) {
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printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ",
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PCI[i].VendorID,
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PCI[i].DeviceID,
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PCI[i].BaseAddress10Len,
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PCI[i].BaseAddress14Len,
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PCI[i].BaseAddress18Len,
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PCI[i].BaseAddress1CLen,
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PCI[i].BaseAddress20Len,
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PCI[i].BaseAddress24Len,
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PCI[i].ROMBaseAddressLen);
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for (index = 0; index < NumDevices; index++) {
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if (DeviceIndex[index] == i)
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break;
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}
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if (index < NumDevices)
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printk("<- %d\n", index);
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else
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printk("\n");
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}
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printk("\n");
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printk("Displaying enumeration of %d bridge devices\n",NumBridges);
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printk("\n");
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printk("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n");
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for (i = 0; i < NumBridges; i++) {
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info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]];
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printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n",
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info->VendorID,
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info->DeviceID,
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info->PrimaryBusNumber,
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info->SecondayBusNumber,
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info->SubordinateBusNumber,
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((u16)info->IOBase << 8) & 0xF000,
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info->IOLimit ?
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((u16)info->IOLimit << 8) | 0xFFF : 0,
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((u32)info->MemoryBase << 16) & 0xFFF00000,
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info->MemoryLimit ?
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((u32)info->MemoryLimit << 16) | 0xFFFFF : 0,
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((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000,
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info->PrefetchableMemoryLimit ?
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((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0,
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info->BridgeControl);
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}
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printk("\n");
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}
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/****************************************************************************
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RETURNS:
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Number of display devices found.
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REMARKS:
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This function enumerates the number of available display devices on the
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PCI bus, and returns the number found.
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****************************************************************************/
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static int PCI_enumerateDevices(void)
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{
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int i,j;
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PCIBridgeInfo *info;
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/* If this is the first time we have been called, enumerate all */
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/* devices on the PCI bus. */
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if (NumPCI == -1) {
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for (i = 0; i < MAX_PCI_DEVICES; i++)
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PCI[i].dwSize = sizeof(PCI[i]);
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if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0)
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return -1;
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/* Build a list of all PCI bridge devices */
|
|
for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) {
|
|
if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) {
|
|
if (NumBridges < MAX_PCI_DEVICES)
|
|
BridgeIndex[NumBridges++] = i;
|
|
}
|
|
}
|
|
|
|
/* Now build a list of all display class devices */
|
|
for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) {
|
|
if (PCI_IS_DISPLAY_CLASS(&PCI[i])) {
|
|
if ((PCI[i].Command & 0x3) == 0x3) {
|
|
DeviceIndex[0] = i;
|
|
}
|
|
else {
|
|
if (NumDevices < MAX_PCI_DEVICES)
|
|
DeviceIndex[NumDevices++] = i;
|
|
}
|
|
if (PCI[i].slot.p.Bus != 0) {
|
|
/* This device is on a different bus than the primary */
|
|
/* PCI bus, so it is probably an AGP device. Find the */
|
|
/* AGP bus device that controls that bus so we can */
|
|
/* control it. */
|
|
for (j = 0; j < NumBridges; j++) {
|
|
info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]];
|
|
if (info->SecondayBusNumber == PCI[i].slot.p.Bus) {
|
|
AGPBridge = info;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Enumerate all PCI and bridge devices to log file */
|
|
EnumeratePCI();
|
|
}
|
|
return NumDevices;
|
|
}
|
|
|
|
FILE *logfile;
|
|
|
|
void printk(const char *fmt, ...)
|
|
{
|
|
va_list argptr;
|
|
va_start(argptr, fmt);
|
|
vfprintf(logfile, fmt, argptr);
|
|
fflush(logfile);
|
|
va_end(argptr);
|
|
}
|
|
|
|
int main(int argc,char *argv[])
|
|
{
|
|
while (argc > 1) {
|
|
if (stricmp(argv[1],"-usev86") == 0) {
|
|
useV86 = true;
|
|
}
|
|
else if (stricmp(argv[1],"-force") == 0) {
|
|
forcePost = true;
|
|
}
|
|
#ifdef DEBUG
|
|
else if (stricmp(argv[1],"-decode") == 0) {
|
|
debugFlags |= DEBUG_DECODE_F;
|
|
}
|
|
else if (stricmp(argv[1],"-iotrace") == 0) {
|
|
debugFlags |= DEBUG_IO_TRACE_F;
|
|
}
|
|
#endif
|
|
else {
|
|
printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n");
|
|
exit(-1);
|
|
}
|
|
argc--;
|
|
argv++;
|
|
}
|
|
if ((logfile = fopen("warmboot.log","w")) == NULL)
|
|
exit(1);
|
|
|
|
PM_init();
|
|
if (!useV86) {
|
|
/* Initialise the x86 BIOS emulator */
|
|
BE_init(false,debugFlags,65536,&VGAInfo[0]);
|
|
}
|
|
|
|
/* Enumerate all devices (which POST's them at the same time) */
|
|
if (PCI_enumerateDevices() < 1) {
|
|
printk("No PCI display devices found!\n");
|
|
return -1;
|
|
}
|
|
|
|
/* Post all the display controller BIOS'es */
|
|
PCI_postControllers();
|
|
|
|
/* Cleanup and exit the emulator */
|
|
if (!useV86)
|
|
BE_exit();
|
|
fclose(logfile);
|
|
return 0;
|
|
}
|