580 lines
14 KiB
ArmAsm
580 lines
14 KiB
ArmAsm
/*
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* U-boot - start.S Startup file of u-boot for BF537
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* This file is based on head.S
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* Copyright (c) 2003 Metrowerks/Motorola
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* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
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* Kenneth Albanowski <kjahds@kjahds.com>,
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* The Silver Hammer Group, Ltd.
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* (c) 1995, Dionne & Associates
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* (c) 1995, DKG Display Tech.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* Note: A change in this file subsequently requires a change in
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* board/$(board_name)/config.mk for a valid u-boot.bin
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*/
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#define ASSEMBLY
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#include <linux/config.h>
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#include <config.h>
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#include <asm/blackfin.h>
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.global _stext;
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.global __bss_start;
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.global start;
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.global _start;
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.global _rambase;
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.global _ramstart;
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.global _ramend;
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.global _bf533_data_dest;
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.global _bf533_data_size;
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.global edata;
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.global _initialize;
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.global _exit;
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.global flashdataend;
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.global init_sdram;
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.global _icache_enable;
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.global _dcache_enable;
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#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
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.global _memory_post_test;
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.global _post_flag;
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#endif
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#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
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#if (CONFIG_CCLK_DIV == 1)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
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#endif
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#if (CONFIG_CCLK_DIV == 2)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
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#endif
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#if (CONFIG_CCLK_DIV == 4)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
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#endif
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#if (CONFIG_CCLK_DIV == 8)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
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#endif
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#ifndef CONFIG_CCLK_ACT_DIV
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#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
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#endif
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#endif
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.text
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_start:
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start:
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_stext:
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R0 = 0x32;
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SYSCFG = R0;
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SSYNC;
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/* As per HW reference manual DAG registers,
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* DATA and Address resgister shall be zero'd
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* in initialization, after a reset state
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*/
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r1 = 0; /* Data registers zero'd */
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r2 = 0;
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r3 = 0;
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r4 = 0;
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r5 = 0;
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r6 = 0;
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r7 = 0;
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p0 = 0; /* Address registers zero'd */
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p1 = 0;
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p2 = 0;
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p3 = 0;
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p4 = 0;
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p5 = 0;
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i0 = 0; /* DAG Registers zero'd */
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i1 = 0;
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i2 = 0;
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i3 = 0;
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m0 = 0;
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m1 = 0;
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m3 = 0;
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m3 = 0;
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l0 = 0;
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l1 = 0;
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l2 = 0;
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l3 = 0;
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b0 = 0;
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b1 = 0;
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b2 = 0;
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b3 = 0;
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/* Set loop counters to zero, to make sure that
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* hw loops are disabled.
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*/
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r0 = 0;
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lc0 = r0;
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lc1 = r0;
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SSYNC;
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/* Check soft reset status */
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p0.h = SWRST >> 16;
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p0.l = SWRST & 0xFFFF;
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r0.l = w[p0];
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cc = bittst(r0, 15);
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if !cc jump no_soft_reset;
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/* Clear Soft reset */
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r0 = 0x0000;
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w[p0] = r0;
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ssync;
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no_soft_reset:
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nop;
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/* Clear EVT registers */
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p0.h = (EVT_EMULATION_ADDR >> 16);
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p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
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p0 += 8;
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p1 = 14;
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r1 = 0;
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LSETUP(4,4) lc0 = p1;
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[ p0 ++ ] = r1;
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#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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r0.l = 0x1;
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w[p0] = r0.l;
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SSYNC;
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#endif
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#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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r0.l = 0x1;
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w[p0] = r0.l;
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SSYNC;
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/*
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* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
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*/
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p0.h = hi(PLL_LOCKCNT);
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p0.l = lo(PLL_LOCKCNT);
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r0 = 0x300(Z);
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w[p0] = r0.l;
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ssync;
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/*
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* Put SDRAM in self-refresh, incase anything is running
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*/
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITSET (R0, 24);
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[P2] = R0;
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SSYNC;
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/*
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* Set PLL_CTL with the value that we calculate in R0
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* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
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* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
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* - [7] = output delay (add 200ps of delay to mem signals)
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* - [6] = input delay (add 200ps of input delay to mem signals)
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* - [5] = PDWN : 1=All Clocks off
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* - [3] = STOPCK : 1=Core Clock off
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* - [1] = PLL_OFF : 1=Disable Power to PLL
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* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
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* all other bits set to zero
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*/
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r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
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r0 = r0 << 9; /* Shift it over, */
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r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
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r0 = r1 | r0;
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r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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cli r2; /* Disable interrupts */
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ssync;
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w[p0] = r0.l; /* Set the value */
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idle; /* Wait for the PLL to stablize */
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sti r2; /* Enable interrupts */
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check_again:
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p0.h = hi(PLL_STAT);
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p0.l = lo(PLL_STAT);
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R0 = W[P0](Z);
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CC = BITTST(R0,5);
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if ! CC jump check_again;
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/* Configure SCLK & CCLK Dividers */
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r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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p0.h = hi(PLL_DIV);
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p0.l = lo(PLL_DIV);
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w[p0] = r0.l;
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ssync;
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#endif
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/*
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* We now are running at speed, time to set the Async mem bank wait states
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* This will speed up execution, since we are normally running from FLASH.
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* we need to read MAC address from FLASH
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*/
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p2.h = (EBIU_AMBCTL1 >> 16);
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p2.l = (EBIU_AMBCTL1 & 0xFFFF);
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r0.h = (AMBCTL1VAL >> 16);
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r0.l = (AMBCTL1VAL & 0xFFFF);
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[p2] = r0;
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ssync;
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p2.h = (EBIU_AMBCTL0 >> 16);
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p2.l = (EBIU_AMBCTL0 & 0xFFFF);
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r0.h = (AMBCTL0VAL >> 16);
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r0.l = (AMBCTL0VAL & 0xFFFF);
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[p2] = r0;
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ssync;
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p2.h = (EBIU_AMGCTL >> 16);
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p2.l = (EBIU_AMGCTL & 0xffff);
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r0 = AMGCTLVAL;
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w[p2] = r0;
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ssync;
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#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
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sp.l = (0xffb01000 & 0xFFFF);
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sp.h = (0xffb01000 >> 16);
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call init_sdram;
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#endif
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#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
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/* DMA POST code to Hi of L1 SRAM */
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postcopy:
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/* P1 Points to the beginning of SYSTEM MMR Space */
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P1.H = hi(SYSMMR_BASE);
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P1.L = lo(SYSMMR_BASE);
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R0.H = _text_l1;
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R0.L = _text_l1;
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R1.H = _etext_l1;
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R1.L = _etext_l1;
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R2 = R1 - R0; /* Count */
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R0.H = _etext;
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R0.L = _etext;
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R1.H = (CFG_MONITOR_BASE >> 16);
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R1.L = (CFG_MONITOR_BASE & 0xFFFF);
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R0 = R0 - R1;
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R1.H = (CFG_FLASH_BASE >> 16);
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R1.L = (CFG_FLASH_BASE & 0xFFFF);
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R0 = R0 + R1; /* Source Address */
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R1.H = hi(L1_ISRAM); /* Destination Address (high) */
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R1.L = lo(L1_ISRAM); /* Destination Address (low) */
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R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
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/* Destination DMAConfig Value (8-bit words) */
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R4.L = (DI_EN | WNR | DMAEN);
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R6 = 0x1 (Z);
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W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
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W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
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[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
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W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
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/* Set Source DMAConfig = DMA Enable,
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Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
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W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
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[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
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W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
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/* Set Destination DMAConfig = DMA Enable,
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Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
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W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
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POST_DMA_DONE:
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p0.h = hi(MDMA_D0_IRQ_STATUS);
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p0.l = lo(MDMA_D0_IRQ_STATUS);
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R0 = W[P0](Z);
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CC = BITTST(R0, 0);
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if ! CC jump POST_DMA_DONE
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R0 = 0x1;
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W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
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/* DMA POST data to Hi of L1 SRAM */
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R0.H = _rodata_l1;
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R0.L = _rodata_l1;
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R1.H = _erodata_l1;
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R1.L = _erodata_l1;
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R2 = R1 - R0; /* Count */
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R0.H = _erodata;
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R0.L = _erodata;
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R1.H = (CFG_MONITOR_BASE >> 16);
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R1.L = (CFG_MONITOR_BASE & 0xFFFF);
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R0 = R0 - R1;
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R1.H = (CFG_FLASH_BASE >> 16);
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R1.L = (CFG_FLASH_BASE & 0xFFFF);
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R0 = R0 + R1; /* Source Address */
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R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
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R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
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R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
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R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
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R6 = 0x1 (Z);
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W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
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W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
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[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
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W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
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/* Set Source DMAConfig = DMA Enable,
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Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
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W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
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[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
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W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
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/* Set Destination DMAConfig = DMA Enable,
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Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
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W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
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POST_DATA_DMA_DONE:
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p0.h = hi(MDMA_D0_IRQ_STATUS);
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p0.l = lo(MDMA_D0_IRQ_STATUS);
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R0 = W[P0](Z);
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CC = BITTST(R0, 0);
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if ! CC jump POST_DATA_DMA_DONE
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R0 = 0x1;
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W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
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p0.l = _memory_post_test;
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p0.h = _memory_post_test;
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r0 = 0x0;
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call (p0);
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r7 = r0; /* save return value */
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call init_sdram;
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#endif
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/* relocate into to RAM */
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call get_pc;
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offset:
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r2.l = offset;
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r2.h = offset;
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r3.l = start;
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r3.h = start;
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r1 = r2 - r3;
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r0 = r0 - r1;
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p1 = r0;
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p2.l = (CFG_MONITOR_BASE & 0xffff);
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p2.h = (CFG_MONITOR_BASE >> 16);
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p3 = 0x04;
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p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
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p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
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loop1:
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r1 = [p1 ++ p3];
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[p2 ++ p3] = r1;
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cc=p2==p4;
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if !cc jump loop1;
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/*
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* configure STACK
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*/
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r0.h = (CONFIG_STACKBASE >> 16);
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r0.l = (CONFIG_STACKBASE & 0xFFFF);
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sp = r0;
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fp = sp;
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/*
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* This next section keeps the processor in supervisor mode
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* during kernel boot. Switches to user mode at end of boot.
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* See page 3-9 of Hardware Reference manual for documentation.
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*/
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/* To keep ourselves in the supervisor mode */
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p0.l = (EVT_IVG15_ADDR & 0xFFFF);
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p0.h = (EVT_IVG15_ADDR >> 16);
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p1.l = _real_start;
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p1.h = _real_start;
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[p0] = p1;
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p0.l = (IMASK & 0xFFFF);
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p0.h = (IMASK >> 16);
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r0.l = LO(IVG15_POS);
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r0.h = HI(IVG15_POS);
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[p0] = r0;
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raise 15;
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p0.l = WAIT_HERE;
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p0.h = WAIT_HERE;
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reti = p0;
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rti;
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WAIT_HERE:
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jump WAIT_HERE;
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.global _real_start;
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_real_start:
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[ -- sp ] = reti;
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#ifdef CONFIG_BF537
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/* Initialise General-Purpose I/O Modules on BF537
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* Rev 0.0 Anomaly 05000212 - PORTx_FER,
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* PORT_MUX Registers Do Not accept "writes" correctly
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*/
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p0.h = hi(PORTF_FER);
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p0.l = lo(PORTF_FER);
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R0.L = W[P0]; /* Read */
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nop;
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nop;
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nop;
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ssync;
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R0 = 0x000F(Z);
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W[P0] = R0.L; /* Write */
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nop;
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nop;
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nop;
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ssync;
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W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
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nop;
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nop;
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nop;
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ssync;
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p0.h = hi(PORTH_FER);
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p0.l = lo(PORTH_FER);
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R0.L = W[P0]; /* Read */
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nop;
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nop;
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nop;
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ssync;
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R0 = 0xFFFF(Z);
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W[P0] = R0.L; /* Write */
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nop;
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nop;
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nop;
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ssync;
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W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
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nop;
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nop;
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nop;
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ssync;
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#endif
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|
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|
/* DMA reset code to Hi of L1 SRAM */
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copy:
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|
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
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P1.L = lo(SYSMMR_BASE);
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|
|
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R0.H = reset_start; /* Source Address (high) */
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R0.L = reset_start; /* Source Address (low) */
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R1.H = reset_end;
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R1.L = reset_end;
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|
R2 = R1 - R0; /* Count */
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|
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
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R1.L = lo(L1_ISRAM); /* Destination Address (low) */
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R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
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R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
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|
|
|
DMA:
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R6 = 0x1 (Z);
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|
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
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W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
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|
|
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[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
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|
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
|
|
/* Set Source DMAConfig = DMA Enable,
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|
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
|
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
|
|
|
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
|
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
|
/* Set Destination DMAConfig = DMA Enable,
|
|
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
|
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
|
|
|
WAIT_DMA_DONE:
|
|
p0.h = hi(MDMA_D0_IRQ_STATUS);
|
|
p0.l = lo(MDMA_D0_IRQ_STATUS);
|
|
R0 = W[P0](Z);
|
|
CC = BITTST(R0, 0);
|
|
if ! CC jump WAIT_DMA_DONE
|
|
|
|
R0 = 0x1;
|
|
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
|
|
|
/* Initialize BSS Section with 0 s */
|
|
p1.l = __bss_start;
|
|
p1.h = __bss_start;
|
|
p2.l = _end;
|
|
p2.h = _end;
|
|
r1 = p1;
|
|
r2 = p2;
|
|
r3 = r2 - r1;
|
|
r3 = r3 >> 2;
|
|
p3 = r3;
|
|
lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
|
|
CC = p2<=p1;
|
|
if CC jump _clear_bss_skip;
|
|
r0 = 0;
|
|
_clear_bss:
|
|
_clear_bss_end:
|
|
[p1++] = r0;
|
|
_clear_bss_skip:
|
|
|
|
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
|
p0.l = _post_flag;
|
|
p0.h = _post_flag;
|
|
r0 = r7;
|
|
[p0] = r0;
|
|
#endif
|
|
|
|
p0.l = _start1;
|
|
p0.h = _start1;
|
|
jump (p0);
|
|
|
|
reset_start:
|
|
p0.h = WDOG_CNT >> 16;
|
|
p0.l = WDOG_CNT & 0xffff;
|
|
r0 = 0x0010;
|
|
w[p0] = r0;
|
|
p0.h = WDOG_CTL >> 16;
|
|
p0.l = WDOG_CTL & 0xffff;
|
|
r0 = 0x0000;
|
|
w[p0] = r0;
|
|
reset_wait:
|
|
jump reset_wait;
|
|
|
|
reset_end:
|
|
nop;
|
|
|
|
_exit:
|
|
jump.s _exit;
|
|
get_pc:
|
|
r0 = rets;
|
|
rts;
|