206 lines
7.0 KiB
C
206 lines
7.0 KiB
C
/*
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* (C) 2010 by Tieto <www.tieto.com>
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* Krzysztof Antonowicz <krzysztof.antonowicz@tieto.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef MTK_MSDC_H
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#define MTK_MSDC_H
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/*
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* Register definitions
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*/
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/* MS/SD Memory Card Controller Configuration Register */
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#define MTK_MSDC_CFG (MTK_MSDC_BASE + 0x0000)
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/* MS/SD Memory Card Controller Status Register MSDC_STA */
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#define MTK_MSDC_STA (MTK_MSDC_BASE + 0x0004)
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/* MS/SD Memory Card Controller Interrupt Register MSDC_INT */
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#define MTK_MSDC_INT (MTK_MSDC_BASE + 0x0008)
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/* MS/SD Memory Card Controller Data Register MSDC_DAT */
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#define MTK_MSDC_DAT (MTK_MSDC_BASE + 0x000C)
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/* MS/SD Memory Card Pin Status Register MSDC_PS */
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#define MTK_MSDC_PS (MTK_MSDC_BASE + 0x0010)
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/* MS/SD Memory Card Controller IO Control Register MSDC_IOCON */
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#define MTK_MSDC_IOCON (MTK_MSDC_BASE + 0x0014)
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/* SD Memory Card Controller Configuration Register SDC_CFG */
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#define MTK_MSDC_SDC_CFG (MTK_MSDC_BASE + 0x0020)
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/* SD Memory Card Controller Command Register SDC_CMD */
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#define MTK_MSDC_SDC_CMD (MTK_MSDC_BASE + 0x0024)
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/* SD Memory Card Controller Argument Register SDC_ARG */
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#define MTK_MSDC_SDC_ARG (MTK_MSDC_BASE + 0x0028)
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/* SD Memory Card Controller Status Register SDC_STA */
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#define MTK_MSDC_SDC_STA (MTK_MSDC_BASE + 0x002C)
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/* SD Memory Card Controller Response Register 0 SDC_RESP0 */
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#define MTK_MSDC_SDC_RESP0 (MTK_MSDC_BASE + 0x0030)
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/* SD Memory Card Controller Response Register 1 SDC_RESP1 */
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#define MTK_MSDC_SDC_RESP1 (MTK_MSDC_BASE + 0x0034)
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/* SD Memory Card Controller Response Register 2 SDC_RESP2 */
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#define MTK_MSDC_SDC_RESP2 (MTK_MSDC_BASE + 0x0038)
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/* SD Memory Card Controller Response Register 3 SDC_RESP3 */
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#define MTK_MSDC_SDC_RESP3 (MTK_MSDC_BASE + 0x003C)
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/* SD Memory Card Controller Command Status Register SDC_CMDSTA */
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#define MTK_MSDC_SDC_CMDSTA (MTK_MSDC_BASE + 0x0040)
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/* SD Memory Card Controller Data Status Register SDC_DATSTA */
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#define MTK_MSDC_SDC_DATSTA (MTK_MSDC_BASE + 0x0044)
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/* SD Memory Card Status Register SDC_CSTA */
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#define MTK_MSDC_SDC_CSTA (MTK_MSDC_BASE + 0x0048)
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/* SD Memory Card IRQ Mask Register 0 SDC_IRQMASK0 */
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#define MTK_MSDC_SDC_IRQMASK0 (MTK_MSDC_BASE + 0x004C)
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/* SD Memory Card IRQ Mask Register 1 SDC_IRQMASK1 */
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#define MTK_MSDC_SDC_IRQMASK1 (MTK_MSDC_BASE + 0x0050)
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/* SDIO Configuration Register SDIO_CFG */
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#define MTK_MSDC_SDIO_CFG (MTK_MSDC_BASE + 0x0054)
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/* SDIO Status Register SDIO_STA */
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#define MTK_MSDC_SDIO_STA (MTK_MSDC_BASE + 0x0058)
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/* Memory Stick Controller Configuration Register MSC_CFG */
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#define MTK_MSDC_MSC_CFG (MTK_MSDC_BASE + 0x0060)
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/* Memory Stick Controller Command Register MSC_CMD */
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#define MTK_MSDC_MSC_CMD (MTK_MSDC_BASE + 0x0064)
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/* Memory Stick Controller Auto Command Register MSC_ACMD */
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#define MTK_MSDC_MSC_ACMD (MTK_MSDC_BASE + 0x0068)
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/* Memory Stick Controller Status Register MSC_STA */
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#define MTK_MSDC_MSC_STA (MTK_MSDC_BASE + 0x006C)
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/* MSDC_CFG bit field definitions */
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#define MTK_MSDC_CFG_MSDC (1 << 0)
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#define MTK_MSDC_CFG_NOCRC (1 << 2)
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#define MTK_MSDC_CFG_RST (1 << 3)
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#define MTK_MSDC_CFG_CLKSRC (1 << 4)
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#define MTK_MSDC_CFG_STDBY (1 << 5)
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#define MTK_MSDC_CFG_RED (1 << 6)
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#define MTK_MSDC_CFG_SCLKON (1 << 7)
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#define MTK_MSDC_CFG_SCLKF 8
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#define MTK_MSDC_CFG_SCLKF_MASK (0xFF << MTK_MSDC_CFG_SCLKF)
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#define MTK_MSDC_CFG_INTEN (1 << 16)
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#define MTK_MSDC_CFG_DMAEN (1 << 17)
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#define MTK_MSDC_CFG_PINEN (1 << 18)
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#define MTK_MSDC_CFG_DIRQEN (1 << 19)
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#define MTK_MSDC_CFG_RCDEN (1 << 20)
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#define MTK_MSDC_CFG_VDDP (1 << 21)
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/* MSDC_SDC_CFG bit field definitions */
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#define MTK_MSDC_SDC_CFG_SIEN (1 << 16)
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#define MTK_MSDC_SDC_CFG_MDLEN (1 << 17)
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#define MTK_MSDC_SDC_CFG_MDLW8 (1 << 18)
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#define MTK_MSDC_SDC_CFG_SDIO (1 << 19)
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#define MTK_MSDC_SDC_CFG_BSYDLY 12
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#define MTK_MSDC_SDC_CFG_BLKLEN_MASK 0x00000FFF
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/* MSDC_SDC_CMD bit field definitions */
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#define MTK_MSDC_SDC_CMD_BREAK (1 << 6)
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#define MTK_MSDC_SDC_CMD_RSPTYP 7
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#define MTK_MSDC_SDC_CMD_RSPTYP_MASK (7 << MTK_MSDC_SDC_CMD_RSPTYP)
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#define MTK_MSDC_SDC_CMD_IDRT (1 << 10)
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#define MTK_MSDC_SDC_CMD_DTYPE 11
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#define MTK_MSDC_SDC_CMD_DTYPE_MASK (3 << MTK_MSDC_SDC_CMD_DTYPE)
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#define MTK_MSDC_SDC_CMD_RW (1 << 13)
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#define MTK_MSDC_SDC_CMD_STOP (1 << 14)
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#define MTK_MSDC_SDC_CMD_INTC (1 << 15)
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#define MTK_MSDC_SDC_CMD_CMDFAIL (1 << 16)
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#define MTK_MSDC_SDC_CMD_CMD_MASK 0x0000003F
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#define MTK_MSDC_SDC_CMD_DTYPE_NO_DATA 0
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#define MTK_MSDC_SDC_CMD_DTYPE_SINGLE_BLOCK 1
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#define MTK_MSDC_SDC_CMD_DTYPE_MULTI_BLOCK 2
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#define MTK_MSDC_SDC_CMD_DTYPE_MULTI_STREAM 3
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#define MTK_MSDC_SDC_CMD_RSPTYP_NONE 0
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#define MTK_MSDC_SDC_CMD_RSPTYP_R1 1
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#define MTK_MSDC_SDC_CMD_RSPTYP_R2 2
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#define MTK_MSDC_SDC_CMD_RSPTYP_R3 3
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#define MTK_MSDC_SDC_CMD_RSPTYP_R4 4
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#define MTK_MSDC_SDC_CMD_RSPTYP_R5 5
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#define MTK_MSDC_SDC_CMD_RSPTYP_R6 6
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#define MTK_MSDC_SDC_CMD_RSPTYP_R1B 7
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/* Possible values of PRCFG0 field - MTK_MSDC_CFG register. */
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#define MTK_MSDC_CFG_PRCFG0_PU_DS_PD_DS (0 << 22)
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#define MTK_MSDC_CFG_PRCFG0_PU_DS_PD_EN (1 << 22)
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#define MTK_MSDC_CFG_PRCFG0_PU_EN_PD_DS (2 << 22)
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#define MTK_MSDC_CFG_PRCFG0_KEEPER (3 << 22)
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/* MSDC_PS bit field definitions */
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#define MTK_MSDC_PS_CDEN (1 << 0)
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#define MTK_MSDC_PS_PIEN0 (1 << 1)
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#define MTK_MSDC_PS_POEN0 (1 << 2)
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#define MTK_MSDC_PS_PIN0 (1 << 3)
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#define MTK_MSDC_PS_PINCHG (1 << 4)
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#define MTK_MSDC_PS_CMD (1 << 24)
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/* MSDC_STA bit field definitions */
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#define MTK_MSDC_STA_BF (1 << 0)
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#define MTK_MSDC_STA_BE (1 << 1)
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#define MTK_MSDC_STA_DRQ (1 << 2)
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#define MTK_MSDC_STA_INT (1 << 3)
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#define MTK_MSDC_STA_FIFOCLR (1 << 14)
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#define MTK_MSDC_STA_BUSY (1 << 15)
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#define MTK_MSDC_STA_FIFOCNT 4
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#define MTK_MSDC_STA_FIFOCNT_MASK 0x00F0
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/* MSDC_SDC_CMDSTA bit field definitions */
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#define MTK_MSDC_SDC_CMDSTA_CMDRDY (1 << 0)
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#define MTK_MSDC_SDC_CMDSTA_CMDTO (1 << 1)
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#define MTK_MSDC_SDC_CMDSTA_RSPCRCERR (1 << 2)
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#define MTK_MSDC_SDC_CMDSTA_MMCIRQ (1 << 3)
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/* MSDC_SDC_DATSTA bit field definitions */
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#define MTK_MSDC_SDC_DATSTA_BLKDONE (1 << 0)
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#define MTK_MSDC_SDC_DATSTA_DATTO (1 << 1)
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#define MTK_MSDC_SDC_DATSTA_DATCRCERR (1 << 2)
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/* MSDC_SDC_STA bit field definitions */
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#define MTK_MSDC_SDC_STA_SDCBUSY (1 << 0)
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#define MTK_MSDC_SDC_STA_CMDBUSY (1 << 1)
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#define MTK_MSDC_SDC_STA_DATBUSY (1 << 2)
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#define MTK_MSDC_SDC_STA_RSV (1 << 3)
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#define MTK_MSDC_SDC_STA_R1BS (1 << 4)
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#define MTK_MSDC_SDC_STA_WP (1 << 15)
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#endif /* MTK_MSDC_H */
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