284 lines
7.5 KiB
C
284 lines
7.5 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop <at> leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/AT91CAP9.h>
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#define MP_BLOCK_3_BASE 0xFDF00000
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91cap9_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
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#endif
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#ifdef CONFIG_USART1
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
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#endif
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#ifdef CONFIG_USART2
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
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#endif
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}
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static void at91cap9_nor_hw_init(void)
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{
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/* Ensure EBI supply is 3.3V */
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AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
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/* Configure SMC CS0 for parallel flash */
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AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
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AT91C_FLASH_NCS_WR_SETUP |
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AT91C_FLASH_NRD_SETUP |
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AT91C_FLASH_NCS_RD_SETUP;
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AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
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AT91C_FLASH_NCS_WR_PULSE |
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AT91C_FLASH_NRD_PULSE |
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AT91C_FLASH_NCS_RD_PULSE;
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AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
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AT91C_FLASH_NRD_CYCLE;
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AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE |
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AT91C_SMC_WRITEMODE |
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AT91C_SMC_NWAITM_NWAIT_DISABLE |
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AT91C_SMC_BAT_BYTE_WRITE |
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AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
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(AT91C_SMC_TDF & (1 << 16));
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}
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#ifdef CONFIG_CMD_NAND
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static void at91cap9_nand_hw_init(void)
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{
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/* Enable CS3 */
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AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
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/* Configure SMC CS3 for NAND/SmartMedia */
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AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
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AT91C_SM_NCS_WR_SETUP |
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AT91C_SM_NRD_SETUP |
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AT91C_SM_NCS_RD_SETUP;
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AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
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AT91C_SM_NCS_WR_PULSE |
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AT91C_SM_NRD_PULSE |
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AT91C_SM_NCS_RD_PULSE;
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AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
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AT91C_SM_NRD_CYCLE;
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AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE |
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AT91C_SMC_WRITEMODE |
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AT91C_SMC_NWAITM_NWAIT_DISABLE |
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AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
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AT91C_SM_TDF;
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
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/* RDY/BSY is not connected */
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/* Enable NandFlash */
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AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
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AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91cap9_spi_hw_init(void)
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{
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AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
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AT91C_PD1_SPI0_NPCS3D;
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
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AT91C_PD1_SPI0_NPCS3D;
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AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
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AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
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AT91C_PA1_SPI0_MOSI |
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AT91C_PA0_SPI0_MISO |
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AT91C_PA3_SPI0_NPCS1 |
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AT91C_PA5_SPI0_NPCS0 |
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AT91C_PA2_SPI0_SPCK;
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
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AT91C_PA4_SPI0_NPCS2A |
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AT91C_PA1_SPI0_MOSI |
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AT91C_PA0_SPI0_MISO |
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AT91C_PA3_SPI0_NPCS1 |
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AT91C_PA5_SPI0_NPCS0 |
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AT91C_PA2_SPI0_SPCK;
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/* Enable Clock */
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91cap9_macb_hw_init(void)
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{
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unsigned int gpio;
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/* Enable clock */
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
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/*
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* Disable pull-up on:
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* RXDV (PB22) => PHY normal mode (not Test mode)
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* ERX0 (PB25) => PHY ADDR0
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* ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
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AT91C_PB25_E_RX0 |
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AT91C_PB26_E_RX1;
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/* Need to reset PHY -> 500ms reset */
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AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
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(AT91C_RSTC_ERSTL & (0x0D << 8)) |
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AT91C_RSTC_URSTEN;
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AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
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AT91C_RSTC_EXTRST;
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/* Wait for end hardware reset */
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while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
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/* Re-enable pull-up */
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AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
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AT91C_PB25_E_RX0 |
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AT91C_PB26_E_RX1;
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#ifdef CONFIG_RMII
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gpio = AT91C_PB30_E_MDIO |
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AT91C_PB29_E_MDC |
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AT91C_PB21_E_TXCK |
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AT91C_PB27_E_RXER |
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AT91C_PB25_E_RX0 |
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AT91C_PB22_E_RXDV |
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AT91C_PB26_E_RX1 |
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AT91C_PB28_E_TXEN |
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AT91C_PB23_E_TX0 |
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AT91C_PB24_E_TX1;
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AT91C_BASE_PIOB->PIO_ASR = gpio;
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AT91C_BASE_PIOB->PIO_BSR = 0;
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AT91C_BASE_PIOB->PIO_PDR = gpio;
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#else
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#error AT91CAP9A-DK works only in RMII mode
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#endif
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/* Unlock EMAC, 3 0 2 1 sequence */
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#define MP_MAC_KEY0 0x5969cb2a
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#define MP_MAC_KEY1 0xb4a1872e
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#define MP_MAC_KEY2 0x05683fbc
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#define MP_MAC_KEY3 0x3634fba4
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#define UNLOCK_MAC 0x00000008
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
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}
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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static void at91cap9_uhp_hw_init(void)
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{
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/* Unlock USB OHCI, 3 2 0 1 sequence */
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#define MP_OHCI_KEY0 0x896c11ca
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#define MP_OHCI_KEY1 0x68ebca21
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#define MP_OHCI_KEY2 0x4823efbc
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#define MP_OHCI_KEY3 0x8651aae4
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#define UNLOCK_OHCI 0x00000010
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91CAP9ADK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91cap9_serial_hw_init();
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at91cap9_nor_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91cap9_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91cap9_spi_hw_init();
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#endif
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#ifdef CONFIG_MACB
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at91cap9_macb_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91cap9_uhp_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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