307 lines
8.2 KiB
C
307 lines
8.2 KiB
C
/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#ifdef CONFIG_NEW_NAND_CODE
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#include <nand.h>
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#include <asm/arch/pxa-regs.h>
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/*
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* hardware specific access to control-lines
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* function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
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*/
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static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd)
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{
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#if 0
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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switch(cmd) {
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case NAND_CTL_SETCLE:
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MACRO_NAND_CTL_SETCLE((unsigned long)base);
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break;
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case NAND_CTL_CLRCLE:
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MACRO_NAND_CTL_CLRCLE((unsigned long)base);
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break;
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case NAND_CTL_SETALE:
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MACRO_NAND_CTL_SETALE((unsigned long)base);
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break;
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case NAND_CTL_CLRALE:
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MACRO_NAND_CTL_CLRALE((unsigned long)base);
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break;
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case NAND_CTL_SETNCE:
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MACRO_NAND_ENABLE_CE((unsigned long)base);
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break;
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case NAND_CTL_CLRNCE:
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MACRO_NAND_DISABLE_CE((unsigned long)base);
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break;
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}
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#endif
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}
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/* read device ready pin */
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static int delta_device_ready(struct mtd_info *mtdinfo)
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{
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if(NDSR & NDSR_RDY)
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return 1;
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else
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return 0;
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#if 0
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struct nand_chip *this = mtdinfo->priv;
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ulong rb_gpio_pin;
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/* use the base addr to find out which chip are we dealing with */
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switch((ulong) this->IO_ADDR_W) {
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case CFG_NAND0_BASE:
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rb_gpio_pin = CFG_NAND0_RDY;
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break;
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case CFG_NAND1_BASE:
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rb_gpio_pin = CFG_NAND1_RDY;
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break;
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default: /* this should never happen */
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return 0;
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break;
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}
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if (in32(GPIO0_IR) & rb_gpio_pin)
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return 1;
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#endif
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return 0;
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}
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static u_char delta_read_byte(struct mtd_info *mtd)
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{
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/* struct nand_chip *this = mtd->priv; */
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unsigned long tmp;
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/* wait for read request */
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while(1) {
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if(NDSR & NDSR_RDDREQ) {
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NDSR |= NDSR_RDDREQ;
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break;
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}
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}
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tmp = NDDB;
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printk("delta_read_byte: 0x%x.\n", tmp);
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return (u_char) tmp;
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}
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/* this is really monahans, not board specific ... */
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static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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/* register struct nand_chip *this = mtd->priv; */
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unsigned long ndcb0=0, ndcb1=0, ndcb2=0;
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uchar command2;
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/* Clear NDSR */
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NDSR = 0xFFF;
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/* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */
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NDCR |= NDCR_ND_RUN;
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/* wait for write command request
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* hmm, might be nice if this could time-out. mk@tbd
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*/
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while(1) {
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if(NDSR & NDSR_WRCMDREQ) {
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NDSR |= NDSR_WRCMDREQ; /* Ack */
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break;
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}
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}
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/* if command is a double byte cmd, we set bit double cmd bit 19 */
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command2 = (command>>8) & 0xFF;
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ndcb0 = command | ((command2 ? 1 : 0) << 19);
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switch (command) {
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case NAND_CMD_READID:
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printk("delta_cmdfunc: NAND_CMD_READID.\n");
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ndcb0 |= ((3 << 21) | (2 << 16));
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break;
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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return;
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default:
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printk("delta_cmdfunc: error, unkown command issued.\n");
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return;
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}
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NDCB0 = ndcb0;
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NDCB1 = ndcb1;
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NDCB2 = ndcb2;
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}
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand_new.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - hwcontrol: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - eccmode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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void board_nand_init(struct nand_chip *nand)
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{
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unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
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/* set up GPIO Control Registers */
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/* turn on the NAND Controller Clock (104 MHz @ D0) */
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CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
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/* NAND Timing Parameters (in ns) */
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#define NAND_TIMING_tCH 10
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#define NAND_TIMING_tCS 0
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#define NAND_TIMING_tWH 20
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#define NAND_TIMING_tWP 40
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#define NAND_TIMING_tRH 20
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#define NAND_TIMING_tRP 40
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#define NAND_TIMING_tR 11123
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#define NAND_TIMING_tWHR 110
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#define NAND_TIMING_tAR 10
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/* Maximum values for NAND Interface Timing Registers in DFC clock
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* periods */
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#define DFC_MAX_tCH 7
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#define DFC_MAX_tCS 7
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#define DFC_MAX_tWH 7
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#define DFC_MAX_tWP 7
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#define DFC_MAX_tRH 7
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#define DFC_MAX_tRP 15
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#define DFC_MAX_tR 65535
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#define DFC_MAX_tWHR 15
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#define DFC_MAX_tAR 15
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#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
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#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
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#define MIN(x, y) ((x < y) ? x : y)
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tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
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DFC_MAX_tCH);
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tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
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DFC_MAX_tCS);
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tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
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DFC_MAX_tWH);
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tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
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DFC_MAX_tWP);
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tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
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DFC_MAX_tRH);
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tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
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DFC_MAX_tRP);
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tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
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DFC_MAX_tR);
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tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
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DFC_MAX_tWHR);
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tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
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DFC_MAX_tAR);
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/* tRP value is split in the register */
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if(tRP & (1 << 4)) {
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tRP_high = 1;
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tRP &= ~(1 << 4);
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} else {
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tRP_high = 0;
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}
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NDTR0CS0 = (tCH << 19) |
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(tCS << 16) |
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(tWH << 11) |
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(tWP << 8) |
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(tRP_high << 6) |
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(tRH << 3) |
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(tRP << 0);
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NDTR1CS0 = (tR << 16) |
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(tWHR << 4) |
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(tAR << 0);
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/* If it doesn't work (unlikely) think about:
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* - ecc enable
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* - chip select don't care
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* - read id byte count
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*
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* Intentionally enabled by not setting bits:
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* - dma (DMA_EN)
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* - page size = 512
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* - cs don't care, see if we can enable later!
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* - row address start position (after second cycle)
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* - pages per block = 32
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*/
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NDCR = (NDCR_ND_ARB_EN | /* enable bus arbiter */
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NDCR_SPARE_EN | /* use the spare area */
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NDCR_DWIDTH_C | /* 16bit DFC data bus width */
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NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
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(2 << 16) | /* read id count = 7 ???? mk@tbd */
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NDCE_RDYM | /* flash device ready ir masked */
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NDCE_CS0_PAGEDM | /* ND_nCSx page done ir masked */
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NDCE_CS1_PAGEDM |
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NDCE_CS0_CMDDM | /* ND_CSx command done ir masked */
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NDCE_CS1_CMDDM |
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NDCE_CS0_BBDM | /* ND_CSx bad block detect ir masked */
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NDCE_CS1_BBDM |
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NDCE_DBERRM | /* double bit error ir masked */
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NDCE_SBERRM | /* single bit error ir masked */
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NDCE_WRDREQM | /* write data request ir masked */
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NDCE_RDDREQM | /* read data request ir masked */
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NDCE_WRCMDREQM); /* write command request ir masked */
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nand->hwcontrol = delta_hwcontrol;
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nand->dev_ready = delta_device_ready;
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nand->eccmode = NAND_ECC_SOFT;
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nand->chip_delay = NAND_DELAY_US;
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nand->options = NAND_BUSWIDTH_16;
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nand->read_byte = delta_read_byte;
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nand->cmdfunc = delta_cmdfunc;
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/* nand->options = NAND_SAMSUNG_LP_OPTIONS; */
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}
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#else
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#error "U-Boot legacy NAND support not available for delta board."
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#endif
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#endif
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