570 lines
17 KiB
C
570 lines
17 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* History
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* 20061201: Wilson Lo (Wilson.Lo@freescale.com)
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* Initialized
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* 20061210: Tanya Jiang (tanya.jiang@freescale.com)
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* Code Cleanup
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* 20070410: Scott Wood <scottwood@freescale.com>
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* More cleanup
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*/
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/*
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* mpc8313epb board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_MPC83XX 1
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#define CONFIG_MPC831X 1
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#define CONFIG_MPC8313 1
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#define CONFIG_MPC8313ERDB 1
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#define CONFIG_PCI
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#define CONFIG_83XX_GENERIC_PCI
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#ifdef CFG_66MHZ
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#elif defined(CFG_33MHZ)
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#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
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#else
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#error Unknown oscillator frequency.
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#endif
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CFG_IMMR 0xE0000000
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#define CFG_MEMTEST_START 0x00001000
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#define CFG_MEMTEST_END 0x07f00000
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/* Early revs of this board will lock up hard when attempting
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* to access the PMC registers, unless a JTAG debugger is
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* connected, or some resistor modifications are made.
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*/
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#define CFG_8313ERDB_BROKEN_PMC 1
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#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* DDR Setup
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*/
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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/*
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* Manually set up DDR parameters, as this board does not
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* seem to have the SPD connected to I2C.
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*/
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#define CFG_DDR_SIZE 128 /* MB */
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#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
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| 0x00040000 /* TODO */ \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
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/* 0x80840102 */
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#define CFG_DDR_TIMING_3 0x00000000
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#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
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| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
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| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
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/* 0x00220802 */
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#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
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| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
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| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
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| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
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| (13 << TIMING_CFG1_REFREC_SHIFT ) \
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| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
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| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
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| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
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/* 0x3935d322 */
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#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
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| (31 << TIMING_CFG2_CPO_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
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| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
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| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
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| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
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/* 0x0f9048ca */ /* P9-45,may need tuning */
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#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
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| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
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/* 0x03200064 */
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#if defined(CONFIG_DDR_2T_TIMING)
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#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
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| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
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| SDRAM_CFG_2T_EN \
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| SDRAM_CFG_DBW_32 )
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#else
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#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
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| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
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| SDRAM_CFG_32_BE )
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/* 0x43080000 */
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#endif
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#define CFG_SDRAM_CFG2 0x00401000;
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/* set burst length to 8 for 32-bit data path */
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#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
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| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
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/* 0x44400232 */
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#define CFG_DDR_MODE_2 0x8000C000;
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#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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/*0x02000000*/
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#define CFG_DDRCDR_VALUE ( DDRCDR_EN \
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| DDRCDR_PZ_NOMZ \
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| DDRCDR_NZ_NOMZ \
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| DDRCDR_M_ODR )
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/*
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* FLASH on the Local Bus
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*/
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
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#define CFG_FLASH_SIZE 8 /* flash size in MB */
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#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
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#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_9 \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD )
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/* 0xFF006FF7 TODO SLOW 16 MB flash size */
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
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#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#endif
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
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#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
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| (0xFF << LBCR_BMT_SHIFT) \
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| 0xF ) /* 0x0004ff0f */
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#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
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/* drivers/nand/nand.c */
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#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */
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#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR )
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/* 0xFFFF8396 */
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#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
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#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
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#define CFG_VSC7385_BASE 0xF0000000
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#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
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#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
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#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
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#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
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#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
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/* local bus read write buffer mapping */
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#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
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#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
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#define CFG_LBLAWBAR3_PRELIM 0xFA000000
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#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
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/* pass open firmware flat tree */
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#define CONFIG_OF_FLAT_TREE 1
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#define CONFIG_OF_BOARD_SETUP 1
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/* maximum size of the flat tree (8K) */
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#define OF_FLAT_TREE_MAX_SIZE 8192
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#define OF_CPU "PowerPC,8313@0"
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#define OF_SOC "soc8313@e0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
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#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/* TSEC */
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
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#define CFG_TSEC2_OFFSET 0x25000
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#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
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#define CONFIG_NET_MULTI
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_MMIO_BASE 0x90000000
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#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
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#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xE2000000
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#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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/*
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* TSEC configuration
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_MPC83XX_TSEC1 1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC83XX_TSEC2 1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0x1c
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#define TSEC2_PHY_ADDR 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_DS1337
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#define CFG_I2C_RTC_ADDR 0x68
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/*
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* Environment
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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/* Address and size of Redundant Environment Sector */
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#else
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \
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| CFG_CMD_PING \
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| CFG_CMD_DHCP \
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| CFG_CMD_I2C \
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| CFG_CMD_MII \
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| CFG_CMD_DATE \
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| CFG_CMD_PCI)
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#define CONFIG_CMDLINE_EDITING 1
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#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \
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~(CFG_CMD_ENV | CFG_CMD_LOADS))
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#if defined(CFG_RAMBOOT)
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#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
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#else
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#define CONFIG_COMMANDS CFG_BASE_COMMANDS
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#endif
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/* Cache Configuration */
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#define CFG_DCACHE_SIZE 16384
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#define CFG_CACHELINE_SIZE 32
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#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
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#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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#ifdef CFG_66MHZ
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/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
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/* 0x62040000 */
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#define CFG_HRCW_LOW (\
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0x20000000 /* reserved, must be set */ |\
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HRCWL_DDRCM |\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2X1)
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#elif defined(CFG_33MHZ)
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/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
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/* 0x65040000 */
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#define CFG_HRCW_LOW (\
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0x20000000 /* reserved, must be set */ |\
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HRCWL_DDRCM |\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_CSB_TO_CLKIN_5X1 |\
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HRCWL_CORE_TO_CSB_2X1)
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#endif
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/* 0xa0606c00 */
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL)
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/* System IO Config */
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#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
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#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
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#define CFG_HID0_INIT 0x000000000
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#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
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#define CFG_HID2 HID2_HBE
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|
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/* DDR @ 0x00000000 */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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|
|
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/* PCI @ 0x80000000 */
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#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10)
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#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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|
|
|
/* PCI2 not supported on 8313 */
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|
#define CFG_IBAT3L (0)
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#define CFG_IBAT3U (0)
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#define CFG_IBAT4L (0)
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#define CFG_IBAT4U (0)
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|
|
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
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|
#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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|
#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
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|
|
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/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
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|
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10)
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|
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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|
|
|
#define CFG_IBAT7L (0)
|
|
#define CFG_IBAT7U (0)
|
|
|
|
#define CFG_DBAT0L CFG_IBAT0L
|
|
#define CFG_DBAT0U CFG_IBAT0U
|
|
#define CFG_DBAT1L CFG_IBAT1L
|
|
#define CFG_DBAT1U CFG_IBAT1U
|
|
#define CFG_DBAT2L CFG_IBAT2L
|
|
#define CFG_DBAT2U CFG_IBAT2U
|
|
#define CFG_DBAT3L CFG_IBAT3L
|
|
#define CFG_DBAT3U CFG_IBAT3U
|
|
#define CFG_DBAT4L CFG_IBAT4L
|
|
#define CFG_DBAT4U CFG_IBAT4U
|
|
#define CFG_DBAT5L CFG_IBAT5L
|
|
#define CFG_DBAT5U CFG_IBAT5U
|
|
#define CFG_DBAT6L CFG_IBAT6L
|
|
#define CFG_DBAT6U CFG_IBAT6U
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
|
|
|
|
#define CONFIG_IPADDR 10.0.0.2
|
|
#define CONFIG_SERVERIP 10.0.0.1
|
|
#define CONFIG_GATEWAYIP 10.0.0.1
|
|
#define CONFIG_NETMASK 255.0.0.0
|
|
#define CONFIG_NETDEV eth1
|
|
|
|
#define CONFIG_HOSTNAME mpc8313erdb
|
|
#define CONFIG_ROOTPATH /nfs/root/path
|
|
#define CONFIG_BOOTFILE uImage
|
|
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
|
#define CONFIG_FDTFILE mpc8313erdb.dtb
|
|
|
|
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
|
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define XMK_STR(x) #x
|
|
#define MK_STR(x) XMK_STR(x)
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
|
"ethprime=TSEC1\0" \
|
|
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
|
"tftpflash=tftpboot $loadaddr $uboot; " \
|
|
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
|
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
|
"fdtaddr=400000\0" \
|
|
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
|
"console=ttyS0\0" \
|
|
"setbootargs=setenv bootargs " \
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv rootdev /dev/nfs;" \
|
|
"run setbootargs;" \
|
|
"run setipargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv rootdev /dev/ram;" \
|
|
"run setbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#undef MK_STR
|
|
#undef XMK_STR
|
|
|
|
#endif /* __CONFIG_H */
|