Dave Liu 3e731aaba3 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave ... In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2010-01-05 13:50:07 -06:00
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ddr	fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave	2010-01-05 13:50:07 -06:00
Makefile	ppc/85xx/86xx: Device tree fixup for number of cores	2009-09-08 09:10:08 -05:00
cpu.c	ppc/p4080: Add various p4080 related defines (and p4040)	2009-09-24 12:05:28 -05:00
fdt.c	ppc/85xx/86xx: Device tree fixup for number of cores	2009-09-08 09:10:08 -05:00
pci_cfg.c	ppc/8xxx: Remove is_fsl_pci_agent	2010-01-05 13:49:07 -06:00